display.vhd

流水灯

Library ieee;
use 	ieee.std_logic_1164.all;
use 	ieee.std_logic_unsigned.all;
use 	IEEE.STD_LOGIC_ARITH.ALL;

--/*************************************************************************
--* COMPONENT NAME:	LCD_DRV
--* DESCRIPTION:	LCD DRIVER
--* FUNCTION:	this component is use to product CPH,OEH,OEV,CKV,VCOM signal and latch the display data
--* PARAMETERS: RGB signal,V,H sync signal 	
--* CALL:		
--* DESIGNER:	Chen Pei Xin			DATE:	2008-5-5
--* MODIFIER:							DATE:				 
--* VERSION：	ver 1.0									
--*************************************************************************/


entity	LCD_DRV	is
	PORT
	(
		N_RST:		in		std_logic;	--display EN signal
		CLK24M:		in		std_logic;	--main clk
		DISMOD:		in		std_logic;	--display mod select 0:256corlor 1:16corlor,now 256 only
		RGB_in:		in		std_logic_vector(7 downto 0);
		
		R_OUT:		out		std_logic_vector(2 downto 0);		--red data out
		G_OUT:		out		std_logic_vector(2 downto 0);		--green	data out
		B_OUT:		out		std_logic_vector(1 downto 0);		--blue	data out
		
		--vSync:		in		std_logic;	--vertical scan sync sign
		hSync:		in		std_logic;	--horizotal scan sync sign,high level valid,must longer than 128 clk
		CKV:		out		std_logic;	--
		OEV:		out		std_logic;	--output enable for scan diver	
		VCOM:		buffer	std_logic;	--comman voltage
		DMOD:		out		std_logic;	--sequential and simultaneous sampling mod select,now for only 	simultaneous
		OEH:		out		std_logic;	--output enable for data diver		
		CPH:		BUFFER		std_logic_vector(2 downto 0)	--sampling and shifting clock
	);
end	LCD_DRV;

architecture Dis of LCD_DRV is
	signal	hSyncTmp:			std_logic;	--for OEH
	signal	R_tmp:			std_logic_vector(2 downto 0);		--red data tmp
	signal	G_tmp:			std_logic_vector(2 downto 0);		--green	data tmp
	signal	B_tmp:			std_logic_vector(1 downto 0);		--blue	data tmp
	signal	sam_clk_cnt: 	std_logic_vector(9 downto 0);		--1440 pulse per ROW but 1600 pulse per HSY
begin

--now only for simultaneous mod
DMOD <= '1';

--RGB_OUT signal must follow the chage of VCOM
R_OUT <= R_tmp when VCOM = '0' else not R_tmp;
B_OUT <= B_tmp when VCOM = '0' else not B_tmp;
G_OUT <= G_tmp when VCOM = '0' else not G_tmp;

--latch the RGB_IN signal and product the CPH signal
sample_cl:	process(CLK24M,N_RST)
begin
	if N_RST = '0' then
		CPH <= "000";
	
	elsif	CLK24M'event and CLK24M = '1' then			
		CPH <= not CPH;		
		
	elsif	CLK24M'event and CLK24M = '0' then		
		R_tmp <= RGB_in(7 downto 5);
		G_tmp <= RGB_in(4 downto 2);
		B_tmp <= RGB_in(1 downto 0);
	end if;
end	process;

--no use
--switch:	process(vSync,N_RST)
--	variable cnt:	std_logic_vector(11 downto 0);
--begin
--	if	vSync'event and vSync = '1' then
--		cnt := cnt + '1';	
--		MD <= cnt(11);	
--	end if;
--end process;

--product the OEV,OEH,VCOM,and CKV signal,make sure the hSync signal is valid longer than 128 clock
OEH <= not(hSyncTmp and hSync);

H_SCAN:	process(CPH(0),hSync)
begin
	
	if hSync = '0' then
		hSyncTmp <= '0';
		OEV <= '0';
		CKV <= '0';			
		sam_clk_cnt <= "0000000000";		
	
	elsif	CPH(0)'event and CPH(0) = '1' then				
		--CPH_CLK
		sam_clk_cnt <= sam_clk_cnt + '1';		
		
		--HSY and OEV PULSE start
		if sam_clk_cnt = "0000000001" then					
			OEV <= '1';			--OEV pulse start 
		end if;	
	
		--OEV pulse width:2.25us = 55.296clk 110111
		--OEH pulse start
		if sam_clk_cnt = "0000011011" then					
			OEV <= '0';			--OEV pulse end 
			hSyncTmp <= '1';	--OEH pulse start 
			VCOM <= not VCOM;	--VCOM pulse
		end if;		
				
		--OEH pulse width:0.5us = 12.3375clk 1100 ,all = 55.296+12.3375 = 67.6335 = 1000100
		--HSV and OEH pulse end
		if sam_clk_cnt = "1010100010" then
			hSyncTmp <= '0';	--OEH pulse end 
		end if;	
		
		--CLKV pulse width:3.5us = 86.3625clk 1100100
		--CLKV pulse start after OEV Tdis2 = 1.5us = 34clk(100101)
		if sam_clk_cnt = "0000010010" then					
			CKV <= '1';			--OEH pulse end 
		end if;			
		if sam_clk_cnt = "0000111101" then					
			CKV <= '0';			--OEH pulse end 
		end if;					
			 
	end if;
end	process;

end Dis;