vga.map.qmsg

流水灯

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 06 15:24:24 2008 " "Info: Processing started: Tue May 06 15:24:24 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vga -c vga " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga -c vga" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LCD_DRV-Dis " "Info: Found design unit 1: LCD_DRV-Dis" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 41 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 LCD_DRV " "Info: Found entity 1: LCD_DRV" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VGAsingl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file VGAsingl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 VGAsingl-behav " "Info: Found design unit 1: VGAsingl-behav" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 VGAsingl " "Info: Found entity 1: VGAsingl" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file vga.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 vga " "Info: Found entity 1: vga" {  } { { "vga.bdf" "" { Schematic "E:/芯片学习/FPGA学习/液晶资料/080505_vga/vga.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "vga " "Info: Elaborating entity \"vga\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "MD VGAsingl inst2 " "Warning: Port \"MD\" of type VGAsingl and instance \"inst2\" is missing source signal" {  } { { "vga.bdf" "" { Schematic "E:/芯片学习/FPGA学习/液晶资料/080505_vga/vga.bdf" { { 184 48 200 280 "inst2" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "DISMOD LCD_DRV inst " "Warning: Port \"DISMOD\" of type LCD_DRV and instance \"inst\" is missing source signal" {  } { { "vga.bdf" "" { Schematic "E:/芯片学习/FPGA学习/液晶资料/080505_vga/vga.bdf" { { 152 416 592 344 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGAsingl VGAsingl:inst2 " "Info: Elaborating entity \"VGAsingl\" for hierarchy \"VGAsingl:inst2\"" {  } { { "vga.bdf" "inst2" { Schematic "E:/芯片学习/FPGA学习/液晶资料/080505_vga/vga.bdf" { { 184 48 200 280 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "GRBX VGAsingl.vhd(31) " "Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(31): signal \"GRBX\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "GRBY VGAsingl.vhd(32) " "Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(32): signal \"GRBY\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "GRBX VGAsingl.vhd(33) " "Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(33): signal \"GRBX\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 33 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "GRBY VGAsingl.vhd(33) " "Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(33): signal \"GRBY\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 33 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LCD_DRV LCD_DRV:inst " "Info: Elaborating entity \"LCD_DRV\" for hierarchy \"LCD_DRV:inst\"" {  } { { "vga.bdf" "inst" { Schematic "E:/芯片学习/FPGA学习/液晶资料/080505_vga/vga.bdf" { { 152 416 592 344 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "VGAsingl:inst2\|MMD\[0\] " "Warning: No clock transition on \"VGAsingl:inst2\|MMD\[0\]\" register due to stuck clock or clock enable" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 24 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "VGAsingl:inst2\|MMD\[0\] clock GND " "Warning: Reduced register \"VGAsingl:inst2\|MMD\[0\]\" with stuck clock port to stuck value GND" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 24 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "VGAsingl:inst2\|MMD\[1\] " "Warning: No clock transition on \"VGAsingl:inst2\|MMD\[1\]\" register due to stuck clock or clock enable" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 24 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "VGAsingl:inst2\|MMD\[1\] clock GND " "Warning: Reduced register \"VGAsingl:inst2\|MMD\[1\]\" with stuck clock port to stuck value GND" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 24 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "LCD_DRV:inst\|CPH\[2\] LCD_DRV:inst\|CPH\[1\] " "Info: Duplicate register \"LCD_DRV:inst\|CPH\[2\]\" merged to single register \"LCD_DRV:inst\|CPH\[1\]\"" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "LCD_DRV:inst\|CPH\[0\] LCD_DRV:inst\|CPH\[1\] " "Info: Duplicate register \"LCD_DRV:inst\|CPH\[0\]\" merged to single register \"LCD_DRV:inst\|CPH\[1\]\"" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "LCD_DRV:inst\|R_tmp\[0\] LCD_DRV:inst\|R_tmp\[2\] " "Info: Duplicate register \"LCD_DRV:inst\|R_tmp\[0\]\" merged to single register \"LCD_DRV:inst\|R_tmp\[2\]\"" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "LCD_DRV:inst\|R_tmp\[1\] LCD_DRV:inst\|R_tmp\[2\] " "Info: Duplicate register \"LCD_DRV:inst\|R_tmp\[1\]\" merged to single register \"LCD_DRV:inst\|R_tmp\[2\]\"" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "LCD_DRV:inst\|G_tmp\[0\] LCD_DRV:inst\|G_tmp\[2\] " "Info: Duplicate register \"LCD_DRV:inst\|G_tmp\[0\]\" merged to single register \"LCD_DRV:inst\|G_tmp\[2\]\"" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "LCD_DRV:inst\|G_tmp\[1\] LCD_DRV:inst\|G_tmp\[2\] " "Info: Duplicate register \"LCD_DRV:inst\|G_tmp\[1\]\" merged to single register \"LCD_DRV:inst\|G_tmp\[2\]\"" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "LCD_DRV:inst\|B_tmp\[0\] LCD_DRV:inst\|B_tmp\[1\] " "Info: Duplicate register \"LCD_DRV:inst\|B_tmp\[0\]\" merged to single register \"LCD_DRV:inst\|B_tmp\[1\]\"" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "DMOD VCC " "Warning: Pin \"DMOD\" stuck at VCC" {  } { { "vga.bdf" "" { Schematic "E:/芯片学习/FPGA学习/液晶资料/080505_vga/vga.bdf" { { 432 720 896 448 "DMOD" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "104 " "Info: Implemented 104 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "85 " "Info: Implemented 85 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 06 15:24:27 2008 " "Info: Processing ended: Tue May 06 15:24:27 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}