vga.fit.qmsg

流水灯

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 06 15:24:28 2008 " "Info: Processing started: Tue May 06 15:24:28 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off vga -c vga " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vga -c vga" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "vga EPM240T100C5 " "Info: Selected device EPM240T100C5 for design \"vga\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Info: Device EPM240T100I5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Info: Device EPM570T100C5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Info: Device EPM570T100I5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in PIN 12 " "Info: Automatically promoted signal \"CLK\" to use Global clock in PIN 12" {  } { { "vga.bdf" "" { Schematic "E:/芯片学习/FPGA学习/液晶资料/080505_vga/vga.bdf" { { 112 104 272 128 "CLK" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "LCD_DRV:inst\|CPH\[1\] Global clock " "Info: Automatically promoted some destinations of signal \"LCD_DRV:inst\|CPH\[1\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CPH\[1\] " "Info: Destination \"CPH\[1\]\" may be non-global or may not use global clock" {  } { { "vga.bdf" "" { Schematic "E:/芯片学习/FPGA学习/液晶资料/080505_vga/vga.bdf" { { 496 720 896 512 "CPH\[2..0\]" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CPH\[0\] " "Info: Destination \"CPH\[0\]\" may be non-global or may not use global clock" {  } { { "vga.bdf" "" { Schematic "E:/芯片学习/FPGA学习/液晶资料/080505_vga/vga.bdf" { { 496 720 896 512 "CPH\[2..0\]" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CPH\[2\] " "Info: Destination \"CPH\[2\]\" may be non-global or may not use global clock" {  } { { "vga.bdf" "" { Schematic "E:/芯片学习/FPGA学习/液晶资料/080505_vga/vga.bdf" { { 496 720 896 512 "CPH\[2..0\]" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LCD_DRV:inst\|CPH\[1\] " "Info: Destination \"LCD_DRV:inst\|CPH\[1\]\" may be non-global or may not use global clock" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "VGAsingl:inst2\|CC\[4\] Global clock " "Info: Automatically promoted some destinations of signal \"VGAsingl:inst2\|CC\[4\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LCD_DRV:inst\|VCOM " "Info: Destination \"LCD_DRV:inst\|VCOM\" may be non-global or may not use global clock" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 34 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LCD_DRV:inst\|OEH~0 " "Info: Destination \"LCD_DRV:inst\|OEH~0\" may be non-global or may not use global clock" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 36 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "VGAsingl:inst2\|Equal~199 " "Info: Destination \"VGAsingl:inst2\|Equal~199\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LCD_DRV:inst\|G_tmp\[2\] " "Info: Destination \"LCD_DRV:inst\|G_tmp\[2\]\" may be non-global or may not use global clock" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "VGAsingl:inst2\|add~344 " "Info: Destination \"VGAsingl:inst2\|add~344\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "VGAsingl:inst2\|GRB\[1\]~373 " "Info: Destination \"VGAsingl:inst2\|GRB\[1\]~373\" may be non-global or may not use global clock" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 17 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "VGAsingl:inst2\|GRB\[1\]~374 " "Info: Destination \"VGAsingl:inst2\|GRB\[1\]~374\" may be non-global or may not use global clock" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 17 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "VGAsingl:inst2\|GRB\[2\]~377 " "Info: Destination \"VGAsingl:inst2\|GRB\[2\]~377\" may be non-global or may not use global clock" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 17 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 46 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "VGAsingl:inst2\|FS\[5\] Global clock " "Info: Automatically promoted some destinations of signal \"VGAsingl:inst2\|FS\[5\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "VGAsingl:inst2\|add~374 " "Info: Destination \"VGAsingl:inst2\|add~374\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "VGAsingl:inst2\|Equal~203 " "Info: Destination \"VGAsingl:inst2\|Equal~203\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 11 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0 0 "Moving registers into LUTs to improve timing and density" 0 0}