vga.tan.qmsg

流水灯

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "LCD_DRV:inst\|CPH\[1\] " "Info: Detected ripple clock \"LCD_DRV:inst\|CPH\[1\]\" as buffer" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LCD_DRV:inst\|CPH\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "VGAsingl:inst2\|FS\[5\] " "Info: Detected ripple clock \"VGAsingl:inst2\|FS\[5\]\" as buffer" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 11 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst2\|FS\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "VGAsingl:inst2\|CC\[4\] " "Info: Detected ripple clock \"VGAsingl:inst2\|CC\[4\]\" as buffer" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 46 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst2\|CC\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register VGAsingl:inst2\|CC\[4\] register LCD_DRV:inst\|R_tmp\[2\] 54.66 MHz 18.296 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 54.66 MHz between source register \"VGAsingl:inst2\|CC\[4\]\" and destination register \"LCD_DRV:inst\|R_tmp\[2\]\" (period= 18.296 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.397 ns + Longest register register " "Info: + Longest register to register delay is 4.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsingl:inst2\|CC\[4\] 1 REG LC_X5_Y1_N1 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N1; Fanout = 17; REG Node = 'VGAsingl:inst2\|CC\[4\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "" { VGAsingl:inst2|CC[4] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.003 ns) + CELL(0.740 ns) 1.743 ns VGAsingl:inst2\|Equal~199 2 COMB LC_X5_Y1_N7 16 " "Info: 2: + IC(1.003 ns) + CELL(0.740 ns) = 1.743 ns; Loc. = LC_X5_Y1_N7; Fanout = 16; COMB Node = 'VGAsingl:inst2\|Equal~199'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "1.743 ns" { VGAsingl:inst2|CC[4] VGAsingl:inst2|Equal~199 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.150 ns) + CELL(0.200 ns) 3.093 ns VGAsingl:inst2\|GRB\[1\]~372 3 COMB LC_X6_Y1_N1 2 " "Info: 3: + IC(1.150 ns) + CELL(0.200 ns) = 3.093 ns; Loc. = LC_X6_Y1_N1; Fanout = 2; COMB Node = 'VGAsingl:inst2\|GRB\[1\]~372'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "1.350 ns" { VGAsingl:inst2|Equal~199 VGAsingl:inst2|GRB[1]~372 } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.713 ns) + CELL(0.591 ns) 4.397 ns LCD_DRV:inst\|R_tmp\[2\] 4 REG LC_X6_Y1_N9 1 " "Info: 4: + IC(0.713 ns) + CELL(0.591 ns) = 4.397 ns; Loc. = LC_X6_Y1_N9; Fanout = 1; REG Node = 'LCD_DRV:inst\|R_tmp\[2\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "1.304 ns" { VGAsingl:inst2|GRB[1]~372 LCD_DRV:inst|R_tmp[2] } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.531 ns ( 34.82 % ) " "Info: Total cell delay = 1.531 ns ( 34.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.866 ns ( 65.18 % ) " "Info: Total interconnect delay = 2.866 ns ( 65.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "4.397 ns" { VGAsingl:inst2|CC[4] VGAsingl:inst2|Equal~199 VGAsingl:inst2|GRB[1]~372 LCD_DRV:inst|R_tmp[2] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "4.397 ns" { VGAsingl:inst2|CC[4] VGAsingl:inst2|Equal~199 VGAsingl:inst2|GRB[1]~372 LCD_DRV:inst|R_tmp[2] } { 0.000ns 1.003ns 1.150ns 0.713ns } { 0.000ns 0.740ns 0.200ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.042 ns - Smallest " "Info: - Smallest clock skew is -4.042 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 10 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 10; CLK Node = 'CLK'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "" { CLK } "NODE_NAME" } "" } } { "vga.bdf" "" { Schematic "E:/芯片学习/FPGA学习/液晶资料/080505_vga/vga.bdf" { { 112 104 272 128 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns LCD_DRV:inst\|R_tmp\[2\] 2 REG LC_X6_Y1_N9 1 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y1_N9; Fanout = 1; REG Node = 'LCD_DRV:inst\|R_tmp\[2\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "2.185 ns" { CLK LCD_DRV:inst|R_tmp[2] } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "3.348 ns" { CLK LCD_DRV:inst|R_tmp[2] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.348 ns" { CLK CLK~combout LCD_DRV:inst|R_tmp[2] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.390 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 7.390 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 10 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 10; CLK Node = 'CLK'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "" { CLK } "NODE_NAME" } "" } } { "vga.bdf" "" { Schematic "E:/芯片学习/FPGA学习/液晶资料/080505_vga/vga.bdf" { { 112 104 272 128 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns VGAsingl:inst2\|FS\[5\] 2 REG LC_X2_Y3_N2 7 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N2; Fanout = 7; REG Node = 'VGAsingl:inst2\|FS\[5\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "2.561 ns" { CLK VGAsingl:inst2|FS[5] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(0.918 ns) 7.390 ns VGAsingl:inst2\|CC\[4\] 3 REG LC_X5_Y1_N1 17 " "Info: 3: + IC(2.748 ns) + CELL(0.918 ns) = 7.390 ns; Loc. = LC_X5_Y1_N1; Fanout = 17; REG Node = 'VGAsingl:inst2\|CC\[4\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "3.666 ns" { VGAsingl:inst2|FS[5] VGAsingl:inst2|CC[4] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 45.67 % ) " "Info: Total cell delay = 3.375 ns ( 45.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.015 ns ( 54.33 % ) " "Info: Total interconnect delay = 4.015 ns ( 54.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "7.390 ns" { CLK VGAsingl:inst2|FS[5] VGAsingl:inst2|CC[4] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.390 ns" { CLK CLK~combout VGAsingl:inst2|FS[5] VGAsingl:inst2|CC[4] } { 0.000ns 0.000ns 1.267ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "3.348 ns" { CLK LCD_DRV:inst|R_tmp[2] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.348 ns" { CLK CLK~combout LCD_DRV:inst|R_tmp[2] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "7.390 ns" { CLK VGAsingl:inst2|FS[5] VGAsingl:inst2|CC[4] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.390 ns" { CLK CLK~combout VGAsingl:inst2|FS[5] VGAsingl:inst2|CC[4] } { 0.000ns 0.000ns 1.267ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 46 -1 0 } } { "display.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/display.vhd" 60 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "4.397 ns" { VGAsingl:inst2|CC[4] VGAsingl:inst2|Equal~199 VGAsingl:inst2|GRB[1]~372 LCD_DRV:inst|R_tmp[2] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "4.397 ns" { VGAsingl:inst2|CC[4] VGAsingl:inst2|Equal~199 VGAsingl:inst2|GRB[1]~372 LCD_DRV:inst|R_tmp[2] } { 0.000ns 1.003ns 1.150ns 0.713ns } { 0.000ns 0.740ns 0.200ns 0.591ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "3.348 ns" { CLK LCD_DRV:inst|R_tmp[2] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.348 ns" { CLK CLK~combout LCD_DRV:inst|R_tmp[2] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "7.390 ns" { CLK VGAsingl:inst2|FS[5] VGAsingl:inst2|CC[4] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.390 ns" { CLK CLK~combout VGAsingl:inst2|FS[5] VGAsingl:inst2|CC[4] } { 0.000ns 0.000ns 1.267ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK vSync VGAsingl:inst2\|LL\[6\] 19.624 ns register " "Info: tco from clock \"CLK\" to destination pin \"vSync\" through register \"VGAsingl:inst2\|LL\[6\]\" is 19.624 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 12.700 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 12.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 10 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 10; CLK Node = 'CLK'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "" { CLK } "NODE_NAME" } "" } } { "vga.bdf" "" { Schematic "E:/芯片学习/FPGA学习/液晶资料/080505_vga/vga.bdf" { { 112 104 272 128 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns VGAsingl:inst2\|FS\[5\] 2 REG LC_X2_Y3_N2 7 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N2; Fanout = 7; REG Node = 'VGAsingl:inst2\|FS\[5\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "2.561 ns" { CLK VGAsingl:inst2|FS[5] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(1.294 ns) 7.766 ns VGAsingl:inst2\|CC\[4\] 3 REG LC_X5_Y1_N1 17 " "Info: 3: + IC(2.748 ns) + CELL(1.294 ns) = 7.766 ns; Loc. = LC_X5_Y1_N1; Fanout = 17; REG Node = 'VGAsingl:inst2\|CC\[4\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "4.042 ns" { VGAsingl:inst2|FS[5] VGAsingl:inst2|CC[4] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.016 ns) + CELL(0.918 ns) 12.700 ns VGAsingl:inst2\|LL\[6\] 4 REG LC_X7_Y1_N7 5 " "Info: 4: + IC(4.016 ns) + CELL(0.918 ns) = 12.700 ns; Loc. = LC_X7_Y1_N7; Fanout = 5; REG Node = 'VGAsingl:inst2\|LL\[6\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "4.934 ns" { VGAsingl:inst2|CC[4] VGAsingl:inst2|LL[6] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 36.76 % ) " "Info: Total cell delay = 4.669 ns ( 36.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.031 ns ( 63.24 % ) " "Info: Total interconnect delay = 8.031 ns ( 63.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "12.700 ns" { CLK VGAsingl:inst2|FS[5] VGAsingl:inst2|CC[4] VGAsingl:inst2|LL[6] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "12.700 ns" { CLK CLK~combout VGAsingl:inst2|FS[5] VGAsingl:inst2|CC[4] VGAsingl:inst2|LL[6] } { 0.000ns 0.000ns 1.267ns 2.748ns 4.016ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.548 ns + Longest register pin " "Info: + Longest register to pin delay is 6.548 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsingl:inst2\|LL\[6\] 1 REG LC_X7_Y1_N7 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y1_N7; Fanout = 5; REG Node = 'VGAsingl:inst2\|LL\[6\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "" { VGAsingl:inst2|LL[6] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "E:/芯片学习/FPGA学习/液晶资料/080505_vga/VGAsingl.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.947 ns) + CELL(0.740 ns) 1.687 ns VGAsingl:inst2\|Equal~198 2 COMB LC_X7_Y1_N8 2 " "Info: 2: + IC(0.947 ns) + CELL(0.740 ns) = 1.687 ns; Loc. = LC_X7_Y1_N8; Fanout = 2; COMB Node = 'VGAsingl:inst2\|Equal~198'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "1.687 ns" { VGAsingl:inst2|LL[6] VGAsingl:inst2|Equal~198 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.740 ns) 3.614 ns VGAsingl:inst2\|LessThan~709 3 COMB LC_X6_Y1_N6 2 " "Info: 3: + IC(1.187 ns) + CELL(0.740 ns) = 3.614 ns; Loc. = LC_X6_Y1_N6; Fanout = 2; COMB Node = 'VGAsingl:inst2\|LessThan~709'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "1.927 ns" { VGAsingl:inst2|Equal~198 VGAsingl:inst2|LessThan~709 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.612 ns) + CELL(2.322 ns) 6.548 ns vSync 4 PIN PIN_47 0 " "Info: 4: + IC(0.612 ns) + CELL(2.322 ns) = 6.548 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'vSync'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "2.934 ns" { VGAsingl:inst2|LessThan~709 vSync } "NODE_NAME" } "" } } { "vga.bdf" "" { Schematic "E:/芯片学习/FPGA学习/液晶资料/080505_vga/vga.bdf" { { 272 720 896 288 "vSync" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.802 ns ( 58.06 % ) " "Info: Total cell delay = 3.802 ns ( 58.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.746 ns ( 41.94 % ) " "Info: Total interconnect delay = 2.746 ns ( 41.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "6.548 ns" { VGAsingl:inst2|LL[6] VGAsingl:inst2|Equal~198 VGAsingl:inst2|LessThan~709 vSync } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "6.548 ns" { VGAsingl:inst2|LL[6] VGAsingl:inst2|Equal~198 VGAsingl:inst2|LessThan~709 vSync } { 0.000ns 0.947ns 1.187ns 0.612ns } { 0.000ns 0.740ns 0.740ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "12.700 ns" { CLK VGAsingl:inst2|FS[5] VGAsingl:inst2|CC[4] VGAsingl:inst2|LL[6] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "12.700 ns" { CLK CLK~combout VGAsingl:inst2|FS[5] VGAsingl:inst2|CC[4] VGAsingl:inst2|LL[6] } { 0.000ns 0.000ns 1.267ns 2.748ns 4.016ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "vga" "UNKNOWN" "V1" "E:/芯片学习/FPGA学习/液晶资料/080505_vga/db/vga.quartus_db" { Floorplan "E:/芯片学习/FPGA学习/液晶资料/080505_vga/" "" "6.548 ns" { VGAsingl:inst2|LL[6] VGAsingl:inst2|Equal~198 VGAsingl:inst2|LessThan~709 vSync } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "6.548 ns" { VGAsingl:inst2|LL[6] VGAsingl:inst2|Equal~198 VGAsingl:inst2|LessThan~709 vSync } { 0.000ns 0.947ns 1.187ns 0.612ns } { 0.000ns 0.740ns 0.740ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 06 15:24:33 2008 " "Info: Processing ended: Tue May 06 15:24:33 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}