📄 vga.fit.rpt
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+--------------------------------------------+------------------------------+
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 2 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 2 ;
; 10 ; 4 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 11) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 2 ;
; 1 Clock ; 8 ;
; 2 Clocks ; 1 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 7.73) ; Number of LABs (Total = 11) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 2 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 2 ;
; 11 ; 2 ;
; 12 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 6.55) ; Number of LABs (Total = 11) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 3 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 3 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 7.55) ; Number of LABs (Total = 11) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 2 ;
; 6 ; 0 ;
; 7 ; 3 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 2 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
Info: Processing started: Tue May 06 15:24:28 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vga -c vga
Info: Selected device EPM240T100C5 for design "vga"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM240T100I5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "CLK" to use Global clock in PIN 12
Info: Automatically promoted some destinations of signal "LCD_DRV:inst|CPH[1]" to use Global clock
Info: Destination "CPH[1]" may be non-global or may not use global clock
Info: Destination "CPH[0]" may be non-global or may not use global clock
Info: Destination "CPH[2]" may be non-global or may not use global clock
Info: Destination "LCD_DRV:inst|CPH[1]" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "VGAsingl:inst2|CC[4]" to use Global clock
Info: Destination "LCD_DRV:inst|VCOM" may be non-global or may not use global clock
Info: Destination "LCD_DRV:inst|OEH~0" may be non-global or may not use global clock
Info: Destination "VGAsingl:inst2|Equal~199" may be non-global or may not use global clock
Info: Destination "LCD_DRV:inst|G_tmp[2]" may be non-global or may not use global clock
Info: Destination "VGAsingl:inst2|add~344" may be non-global or may not use global clock
Info: Destination "VGAsingl:inst2|GRB[1]~373" may be non-global or may not use global clock
Info: Destination "VGAsingl:inst2|GRB[1]~374" may be non-global or may not use global clock
Info: Destination "VGAsingl:inst2|GRB[2]~377" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "VGAsingl:inst2|FS[5]" to use Global clock
Info: Destination "VGAsingl:inst2|add~374" may be non-global or may not use global clock
Info: Destination "VGAsingl:inst2|Equal~203" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 7.223 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y1; Fanout = 5; REG Node = 'VGAsingl:inst2|LL[7]'
Info: 2: + IC(0.443 ns) + CELL(0.914 ns) = 1.357 ns; Loc. = LAB_X7_Y1; Fanout = 2; COMB Node = 'VGAsingl:inst2|Equal~198'
Info: 3: + IC(0.970 ns) + CELL(0.740 ns) = 3.067 ns; Loc. = LAB_X6_Y1; Fanout = 2; COMB Node = 'VGAsingl:inst2|LessThan~708'
Info: 4: + IC(0.342 ns) + CELL(0.914 ns) = 4.323 ns; Loc. = LAB_X6_Y1; Fanout = 2; COMB Node = 'VGAsingl:inst2|LessThan~709'
Info: 5: + IC(0.578 ns) + CELL(2.322 ns) = 7.223 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'vSync'
Info: Total cell delay = 4.890 ns ( 67.70 % )
Info: Total interconnect delay = 2.333 ns ( 32.30 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 3%
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin DMOD has VCC driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Processing ended: Tue May 06 15:24:30 2008
Info: Elapsed time: 00:00:02
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