fir.map.qmsg

17阶FIR滤波器VHDL代码及说明文档 下载立即可以仿真

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult162.vhd(27) " "Warning (10492): VHDL Process Statement warning at mult162.vhd(27): signal \"s3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult162.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult162.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult162.vhd(30) " "Warning (10492): VHDL Process Statement warning at mult162.vhd(30): signal \"s1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult162.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult162.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult162.vhd(30) " "Warning (10492): VHDL Process Statement warning at mult162.vhd(30): signal \"s2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult162.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult162.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult162.vhd(30) " "Warning (10492): VHDL Process Statement warning at mult162.vhd(30): signal \"s3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult162.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult162.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dff15 dff15:inst43 " "Info: Elaborating entity \"dff15\" for hierarchy \"dff15:inst43\"" {  } { { "fir.bdf" "inst43" { Schematic "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/fir.bdf" { { 992 1920 2080 1088 "inst43" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult242 mult242:inst40 " "Info: Elaborating entity \"mult242\" for hierarchy \"mult242:inst40\"" {  } { { "fir.bdf" "inst40" { Schematic "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/fir.bdf" { { 528 2080 2176 680 "inst40" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult242.vhd(29) " "Warning (10492): VHDL Process Statement warning at mult242.vhd(29): signal \"s1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult242.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult242.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult242.vhd(29) " "Warning (10492): VHDL Process Statement warning at mult242.vhd(29): signal \"s2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult242.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult242.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult242.vhd(29) " "Warning (10492): VHDL Process Statement warning at mult242.vhd(29): signal \"s3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult242.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult242.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s4 mult242.vhd(29) " "Warning (10492): VHDL Process Statement warning at mult242.vhd(29): signal \"s4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult242.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult242.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 mult242.vhd(32) " "Warning (10492): VHDL Process Statement warning at mult242.vhd(32): signal \"s1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult242.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult242.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 mult242.vhd(32) " "Warning (10492): VHDL Process Statement warning at mult242.vhd(32): signal \"s2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult242.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult242.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 mult242.vhd(32) " "Warning (10492): VHDL Process Statement warning at mult242.vhd(32): signal \"s3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult242.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult242.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s4 mult242.vhd(32) " "Warning (10492): VHDL Process Statement warning at mult242.vhd(32): signal \"s4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult242.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult242.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dff89 dff89:inst34 " "Info: Elaborating entity \"dff89\" for hierarchy \"dff89:inst34\"" {  } { { "fir.bdf" "inst34" { Schematic "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/fir.bdf" { { 216 1952 2096 312 "inst34" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[0\] dff89:inst34\|Dout\[0\] " "Info: Duplicate register \"dff8:inst10\|Dout\[0\]\" merged to single register \"dff89:inst34\|Dout\[0\]\"" {  } { { "dff8.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/dff8.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[1\] dff89:inst34\|Dout\[1\] " "Info: Duplicate register \"dff8:inst10\|Dout\[1\]\" merged to single register \"dff89:inst34\|Dout\[1\]\"" {  } { { "dff8.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/dff8.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[2\] dff89:inst34\|Dout\[2\] " "Info: Duplicate register \"dff8:inst10\|Dout\[2\]\" merged to single register \"dff89:inst34\|Dout\[2\]\"" {  } { { "dff8.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/dff8.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[3\] dff89:inst34\|Dout\[3\] " "Info: Duplicate register \"dff8:inst10\|Dout\[3\]\" merged to single register \"dff89:inst34\|Dout\[3\]\"" {  } { { "dff8.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/dff8.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[4\] dff89:inst34\|Dout\[4\] " "Info: Duplicate register \"dff8:inst10\|Dout\[4\]\" merged to single register \"dff89:inst34\|Dout\[4\]\"" {  } { { "dff8.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/dff8.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[5\] dff89:inst34\|Dout\[5\] " "Info: Duplicate register \"dff8:inst10\|Dout\[5\]\" merged to single register \"dff89:inst34\|Dout\[5\]\"" {  } { { "dff8.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/dff8.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[6\] dff89:inst34\|Dout\[6\] " "Info: Duplicate register \"dff8:inst10\|Dout\[6\]\" merged to single register \"dff89:inst34\|Dout\[6\]\"" {  } { { "dff8.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/dff8.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff89:inst34\|Dout\[8\] dff89:inst34\|Dout\[7\] " "Info: Duplicate register \"dff89:inst34\|Dout\[8\]\" merged to single register \"dff89:inst34\|Dout\[7\]\"" {  } { { "dff89.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/dff89.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dff8:inst10\|Dout\[7\] dff89:inst34\|Dout\[7\] " "Info: Duplicate register \"dff8:inst10\|Dout\[7\]\" merged to single register \"dff89:inst34\|Dout\[7\]\"" {  } { { "dff8.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/dff8.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "mult162:inst33\|Dout\[0\] data_in GND " "Warning: Reduced register \"mult162:inst33\|Dout\[0\]\" with stuck data_in port to stuck value GND" {  } { { "mult162.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult162.vhd" 36 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "mult52:inst31\|Dout\[0\] data_in GND " "Warning: Reduced register \"mult52:inst31\|Dout\[0\]\" with stuck data_in port to stuck value GND" {  } { { "mult52.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult52.vhd" 36 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "mult12:inst26\|Dout\[0\] data_in GND " "Warning: Reduced register \"mult12:inst26\|Dout\[0\]\" with stuck data_in port to stuck value GND" {  } { { "mult12.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult12.vhd" 32 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "720 " "Info: Implemented 720 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "702 " "Info: Implemented 702 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 47 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 47 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 07 15:50:33 2008 " "Info: Processing ended: Wed May 07 15:50:33 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:26 " "Info: Elapsed time: 00:00:26" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}