fir.fit.qmsg

17阶FIR滤波器VHDL代码及说明文档 下载立即可以仿真

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:09 " "Info: Fitter placement operations ending: elapsed time is 00:00:09" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.882 ns register register " "Info: Estimated most critical path is register to register delay of 7.882 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dff89:inst34\|Dout\[1\] 1 REG LAB_X10_Y5 28 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y5; Fanout = 28; REG Node = 'dff89:inst34\|Dout\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dff89:inst34|Dout[1] } "NODE_NAME" } } { "dff89.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/dff89.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.649 ns) + CELL(0.333 ns) 0.982 ns mult242:inst40\|Add0~203COUT1_225 2 COMB LAB_X9_Y5 2 " "Info: 2: + IC(0.649 ns) + CELL(0.333 ns) = 0.982 ns; Loc. = LAB_X9_Y5; Fanout = 2; COMB Node = 'mult242:inst40\|Add0~203COUT1_225'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.982 ns" { dff89:inst34|Dout[1] mult242:inst40|Add0~203COUT1_225 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.044 ns mult242:inst40\|Add0~201COUT1_227 3 COMB LAB_X9_Y5 2 " "Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 1.044 ns; Loc. = LAB_X9_Y5; Fanout = 2; COMB Node = 'mult242:inst40\|Add0~201COUT1_227'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.062 ns" { mult242:inst40|Add0~203COUT1_225 mult242:inst40|Add0~201COUT1_227 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.106 ns mult242:inst40\|Add0~199COUT1_229 4 COMB LAB_X9_Y5 2 " "Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 1.106 ns; Loc. = LAB_X9_Y5; Fanout = 2; COMB Node = 'mult242:inst40\|Add0~199COUT1_229'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.062 ns" { mult242:inst40|Add0~201COUT1_227 mult242:inst40|Add0~199COUT1_229 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 1.574 ns mult242:inst40\|Add0~196 5 COMB LAB_X9_Y5 2 " "Info: 5: + IC(0.000 ns) + CELL(0.468 ns) = 1.574 ns; Loc. = LAB_X9_Y5; Fanout = 2; COMB Node = 'mult242:inst40\|Add0~196'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.468 ns" { mult242:inst40|Add0~199COUT1_229 mult242:inst40|Add0~196 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.477 ns) + CELL(0.645 ns) 2.696 ns mult242:inst40\|Add1~216 6 COMB LAB_X8_Y5 5 " "Info: 6: + IC(0.477 ns) + CELL(0.645 ns) = 2.696 ns; Loc. = LAB_X8_Y5; Fanout = 5; COMB Node = 'mult242:inst40\|Add1~216'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.122 ns" { mult242:inst40|Add0~196 mult242:inst40|Add1~216 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.523 ns) 3.219 ns mult242:inst40\|Add1~213 7 COMB LAB_X8_Y5 3 " "Info: 7: + IC(0.000 ns) + CELL(0.523 ns) = 3.219 ns; Loc. = LAB_X8_Y5; Fanout = 3; COMB Node = 'mult242:inst40\|Add1~213'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.523 ns" { mult242:inst40|Add1~216 mult242:inst40|Add1~213 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.443 ns) 4.501 ns mult242:inst40\|Add2~363COUT1_419 8 COMB LAB_X9_Y3 2 " "Info: 8: + IC(0.839 ns) + CELL(0.443 ns) = 4.501 ns; Loc. = LAB_X9_Y3; Fanout = 2; COMB Node = 'mult242:inst40\|Add2~363COUT1_419'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.282 ns" { mult242:inst40|Add1~213 mult242:inst40|Add2~363COUT1_419 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 4.563 ns mult242:inst40\|Add2~360COUT1_421 9 COMB LAB_X9_Y3 2 " "Info: 9: + IC(0.000 ns) + CELL(0.062 ns) = 4.563 ns; Loc. = LAB_X9_Y3; Fanout = 2; COMB Node = 'mult242:inst40\|Add2~360COUT1_421'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.062 ns" { mult242:inst40|Add2~363COUT1_419 mult242:inst40|Add2~360COUT1_421 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 4.625 ns mult242:inst40\|Add2~357COUT1_423 10 COMB LAB_X9_Y3 2 " "Info: 10: + IC(0.000 ns) + CELL(0.062 ns) = 4.625 ns; Loc. = LAB_X9_Y3; Fanout = 2; COMB Node = 'mult242:inst40\|Add2~357COUT1_423'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.062 ns" { mult242:inst40|Add2~360COUT1_421 mult242:inst40|Add2~357COUT1_423 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 5.093 ns mult242:inst40\|Add2~353 11 COMB LAB_X9_Y3 1 " "Info: 11: + IC(0.000 ns) + CELL(0.468 ns) = 5.093 ns; Loc. = LAB_X9_Y3; Fanout = 1; COMB Node = 'mult242:inst40\|Add2~353'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.468 ns" { mult242:inst40|Add2~357COUT1_423 mult242:inst40|Add2~353 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.340 ns) 6.069 ns mult242:inst40\|Add2~355 12 COMB LAB_X11_Y3 2 " "Info: 12: + IC(0.636 ns) + CELL(0.340 ns) = 6.069 ns; Loc. = LAB_X11_Y3; Fanout = 2; COMB Node = 'mult242:inst40\|Add2~355'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.976 ns" { mult242:inst40|Add2~353 mult242:inst40|Add2~355 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.477 ns) + CELL(0.645 ns) 7.191 ns mult242:inst40\|Dout\[13\]~70 13 COMB LAB_X10_Y3 1 " "Info: 13: + IC(0.477 ns) + CELL(0.645 ns) = 7.191 ns; Loc. = LAB_X10_Y3; Fanout = 1; COMB Node = 'mult242:inst40\|Dout\[13\]~70'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.122 ns" { mult242:inst40|Add2~355 mult242:inst40|Dout[13]~70 } "NODE_NAME" } } { "mult242.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult242.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.691 ns) 7.882 ns mult242:inst40\|Dout\[14\] 14 REG LAB_X10_Y3 1 " "Info: 14: + IC(0.000 ns) + CELL(0.691 ns) = 7.882 ns; Loc. = LAB_X10_Y3; Fanout = 1; REG Node = 'mult242:inst40\|Dout\[14\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.691 ns" { mult242:inst40|Dout[13]~70 mult242:inst40|Dout[14] } "NODE_NAME" } } { "mult242.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult242.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.804 ns ( 60.95 % ) " "Info: Total cell delay = 4.804 ns ( 60.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.078 ns ( 39.05 % ) " "Info: Total interconnect delay = 3.078 ns ( 39.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.882 ns" { dff89:inst34|Dout[1] mult242:inst40|Add0~203COUT1_225 mult242:inst40|Add0~201COUT1_227 mult242:inst40|Add0~199COUT1_229 mult242:inst40|Add0~196 mult242:inst40|Add1~216 mult242:inst40|Add1~213 mult242:inst40|Add2~363COUT1_419 mult242:inst40|Add2~360COUT1_421 mult242:inst40|Add2~357COUT1_423 mult242:inst40|Add2~353 mult242:inst40|Add2~355 mult242:inst40|Dout[13]~70 mult242:inst40|Dout[14] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 7 " "Info: Average interconnect usage is 4% of the available device resources. Peak interconnect usage is 7%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x27_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x27_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 07 15:52:18 2008 " "Info: Processing ended: Wed May 07 15:52:18 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:59 " "Info: Elapsed time: 00:00:59" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/fir.fit.smsg " "Info: Generated suppressed messages file C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/fir.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}