📄 fir.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "fir.bdf" "" { Schematic "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register dff89:inst34\|Dout\[0\] register mult242:inst40\|Dout\[14\] 125.42 MHz 7.973 ns Internal " "Info: Clock \"clk\" has Internal fmax of 125.42 MHz between source register \"dff89:inst34\|Dout\[0\]\" and destination register \"mult242:inst40\|Dout\[14\]\" (period= 7.973 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.771 ns + Longest register register " "Info: + Longest register to register delay is 7.771 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dff89:inst34\|Dout\[0\] 1 REG LC_X10_Y5_N3 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y5_N3; Fanout = 23; REG Node = 'dff89:inst34\|Dout\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dff89:inst34|Dout[0] } "NODE_NAME" } } { "dff89.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/dff89.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.617 ns) + CELL(0.443 ns) 1.060 ns mult242:inst40\|Add0~203COUT1_225 2 COMB LC_X9_Y5_N0 2 " "Info: 2: + IC(0.617 ns) + CELL(0.443 ns) = 1.060 ns; Loc. = LC_X9_Y5_N0; Fanout = 2; COMB Node = 'mult242:inst40\|Add0~203COUT1_225'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.060 ns" { dff89:inst34|Dout[0] mult242:inst40|Add0~203COUT1_225 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.122 ns mult242:inst40\|Add0~201COUT1_227 3 COMB LC_X9_Y5_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 1.122 ns; Loc. = LC_X9_Y5_N1; Fanout = 2; COMB Node = 'mult242:inst40\|Add0~201COUT1_227'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.062 ns" { mult242:inst40|Add0~203COUT1_225 mult242:inst40|Add0~201COUT1_227 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.184 ns mult242:inst40\|Add0~199COUT1_229 4 COMB LC_X9_Y5_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 1.184 ns; Loc. = LC_X9_Y5_N2; Fanout = 2; COMB Node = 'mult242:inst40\|Add0~199COUT1_229'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.062 ns" { mult242:inst40|Add0~201COUT1_227 mult242:inst40|Add0~199COUT1_229 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 1.652 ns mult242:inst40\|Add0~196 5 COMB LC_X9_Y5_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.468 ns) = 1.652 ns; Loc. = LC_X9_Y5_N3; Fanout = 2; COMB Node = 'mult242:inst40\|Add0~196'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.468 ns" { mult242:inst40|Add0~199COUT1_229 mult242:inst40|Add0~196 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.554 ns) + CELL(0.553 ns) 2.759 ns mult242:inst40\|Add1~216 6 COMB LC_X8_Y5_N4 5 " "Info: 6: + IC(0.554 ns) + CELL(0.553 ns) = 2.759 ns; Loc. = LC_X8_Y5_N4; Fanout = 5; COMB Node = 'mult242:inst40\|Add1~216'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.107 ns" { mult242:inst40|Add0~196 mult242:inst40|Add1~216 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.478 ns) 3.237 ns mult242:inst40\|Add1~213 7 COMB LC_X8_Y5_N5 3 " "Info: 7: + IC(0.000 ns) + CELL(0.478 ns) = 3.237 ns; Loc. = LC_X8_Y5_N5; Fanout = 3; COMB Node = 'mult242:inst40\|Add1~213'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.478 ns" { mult242:inst40|Add1~216 mult242:inst40|Add1~213 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.333 ns) 4.491 ns mult242:inst40\|Add2~363COUT1_419 8 COMB LC_X9_Y3_N1 2 " "Info: 8: + IC(0.921 ns) + CELL(0.333 ns) = 4.491 ns; Loc. = LC_X9_Y3_N1; Fanout = 2; COMB Node = 'mult242:inst40\|Add2~363COUT1_419'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.254 ns" { mult242:inst40|Add1~213 mult242:inst40|Add2~363COUT1_419 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 4.553 ns mult242:inst40\|Add2~360COUT1_421 9 COMB LC_X9_Y3_N2 2 " "Info: 9: + IC(0.000 ns) + CELL(0.062 ns) = 4.553 ns; Loc. = LC_X9_Y3_N2; Fanout = 2; COMB Node = 'mult242:inst40\|Add2~360COUT1_421'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.062 ns" { mult242:inst40|Add2~363COUT1_419 mult242:inst40|Add2~360COUT1_421 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 4.615 ns mult242:inst40\|Add2~357COUT1_423 10 COMB LC_X9_Y3_N3 2 " "Info: 10: + IC(0.000 ns) + CELL(0.062 ns) = 4.615 ns; Loc. = LC_X9_Y3_N3; Fanout = 2; COMB Node = 'mult242:inst40\|Add2~357COUT1_423'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.062 ns" { mult242:inst40|Add2~360COUT1_421 mult242:inst40|Add2~357COUT1_423 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 5.083 ns mult242:inst40\|Add2~353 11 COMB LC_X9_Y3_N4 1 " "Info: 11: + IC(0.000 ns) + CELL(0.468 ns) = 5.083 ns; Loc. = LC_X9_Y3_N4; Fanout = 1; COMB Node = 'mult242:inst40\|Add2~353'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.468 ns" { mult242:inst40|Add2~357COUT1_423 mult242:inst40|Add2~353 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.849 ns) + CELL(0.225 ns) 6.157 ns mult242:inst40\|Add2~355 12 COMB LC_X11_Y3_N9 2 " "Info: 12: + IC(0.849 ns) + CELL(0.225 ns) = 6.157 ns; Loc. = LC_X11_Y3_N9; Fanout = 2; COMB Node = 'mult242:inst40\|Add2~355'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.074 ns" { mult242:inst40|Add2~353 mult242:inst40|Add2~355 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 718 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.519 ns) + CELL(0.449 ns) 7.125 ns mult242:inst40\|Dout\[13\]~70 13 COMB LC_X10_Y3_N4 1 " "Info: 13: + IC(0.519 ns) + CELL(0.449 ns) = 7.125 ns; Loc. = LC_X10_Y3_N4; Fanout = 1; COMB Node = 'mult242:inst40\|Dout\[13\]~70'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.968 ns" { mult242:inst40|Add2~355 mult242:inst40|Dout[13]~70 } "NODE_NAME" } } { "mult242.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult242.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.646 ns) 7.771 ns mult242:inst40\|Dout\[14\] 14 REG LC_X10_Y3_N5 1 " "Info: 14: + IC(0.000 ns) + CELL(0.646 ns) = 7.771 ns; Loc. = LC_X10_Y3_N5; Fanout = 1; REG Node = 'mult242:inst40\|Dout\[14\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.646 ns" { mult242:inst40|Dout[13]~70 mult242:inst40|Dout[14] } "NODE_NAME" } } { "mult242.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult242.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.311 ns ( 55.48 % ) " "Info: Total cell delay = 4.311 ns ( 55.48 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.460 ns ( 44.52 % ) " "Info: Total interconnect delay = 3.460 ns ( 44.52 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.771 ns" { dff89:inst34|Dout[0] mult242:inst40|Add0~203COUT1_225 mult242:inst40|Add0~201COUT1_227 mult242:inst40|Add0~199COUT1_229 mult242:inst40|Add0~196 mult242:inst40|Add1~216 mult242:inst40|Add1~213 mult242:inst40|Add2~363COUT1_419 mult242:inst40|Add2~360COUT1_421 mult242:inst40|Add2~357COUT1_423 mult242:inst40|Add2~353 mult242:inst40|Add2~355 mult242:inst40|Dout[13]~70 mult242:inst40|Dout[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.771 ns" { dff89:inst34|Dout[0] mult242:inst40|Add0~203COUT1_225 mult242:inst40|Add0~201COUT1_227 mult242:inst40|Add0~199COUT1_229 mult242:inst40|Add0~196 mult242:inst40|Add1~216 mult242:inst40|Add1~213 mult242:inst40|Add2~363COUT1_419 mult242:inst40|Add2~360COUT1_421 mult242:inst40|Add2~357COUT1_423 mult242:inst40|Add2~353 mult242:inst40|Add2~355 mult242:inst40|Dout[13]~70 mult242:inst40|Dout[14] } { 0.000ns 0.617ns 0.000ns 0.000ns 0.000ns 0.554ns 0.000ns 0.921ns 0.000ns 0.000ns 0.000ns 0.849ns 0.519ns 0.000ns } { 0.000ns 0.443ns 0.062ns 0.062ns 0.468ns 0.553ns 0.478ns 0.333ns 0.062ns 0.062ns 0.468ns 0.225ns 0.449ns 0.646ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.099 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 435 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 435; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fir.bdf" "" { Schematic "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns mult242:inst40\|Dout\[14\] 2 REG LC_X10_Y3_N5 1 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X10_Y3_N5; Fanout = 1; REG Node = 'mult242:inst40\|Dout\[14\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.969 ns" { clk mult242:inst40|Dout[14] } "NODE_NAME" } } { "mult242.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult242.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.90 % ) " "Info: Total cell delay = 1.677 ns ( 79.90 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns ( 20.10 % ) " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.099 ns" { clk mult242:inst40|Dout[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.099 ns" { clk clk~out0 mult242:inst40|Dout[14] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.099 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 435 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 435; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fir.bdf" "" { Schematic "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns dff89:inst34\|Dout\[0\] 2 REG LC_X10_Y5_N3 23 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X10_Y5_N3; Fanout = 23; REG Node = 'dff89:inst34\|Dout\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.969 ns" { clk dff89:inst34|Dout[0] } "NODE_NAME" } } { "dff89.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/dff89.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.90 % ) " "Info: Total cell delay = 1.677 ns ( 79.90 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns ( 20.10 % ) " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.099 ns" { clk dff89:inst34|Dout[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.099 ns" { clk clk~out0 dff89:inst34|Dout[0] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.099 ns" { clk mult242:inst40|Dout[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.099 ns" { clk clk~out0 mult242:inst40|Dout[14] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.099 ns" { clk dff89:inst34|Dout[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.099 ns" { clk clk~out0 dff89:inst34|Dout[0] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "dff89.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/dff89.vhd" 18 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "mult242.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/mult242.vhd" 38 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.771 ns" { dff89:inst34|Dout[0] mult242:inst40|Add0~203COUT1_225 mult242:inst40|Add0~201COUT1_227 mult242:inst40|Add0~199COUT1_229 mult242:inst40|Add0~196 mult242:inst40|Add1~216 mult242:inst40|Add1~213 mult242:inst40|Add2~363COUT1_419 mult242:inst40|Add2~360COUT1_421 mult242:inst40|Add2~357COUT1_423 mult242:inst40|Add2~353 mult242:inst40|Add2~355 mult242:inst40|Dout[13]~70 mult242:inst40|Dout[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.771 ns" { dff89:inst34|Dout[0] mult242:inst40|Add0~203COUT1_225 mult242:inst40|Add0~201COUT1_227 mult242:inst40|Add0~199COUT1_229 mult242:inst40|Add0~196 mult242:inst40|Add1~216 mult242:inst40|Add1~213 mult242:inst40|Add2~363COUT1_419 mult242:inst40|Add2~360COUT1_421 mult242:inst40|Add2~357COUT1_423 mult242:inst40|Add2~353 mult242:inst40|Add2~355 mult242:inst40|Dout[13]~70 mult242:inst40|Dout[14] } { 0.000ns 0.617ns 0.000ns 0.000ns 0.000ns 0.554ns 0.000ns 0.921ns 0.000ns 0.000ns 0.000ns 0.849ns 0.519ns 0.000ns } { 0.000ns 0.443ns 0.062ns 0.062ns 0.468ns 0.553ns 0.478ns 0.333ns 0.062ns 0.062ns 0.468ns 0.225ns 0.449ns 0.646ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.099 ns" { clk mult242:inst40|Dout[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.099 ns" { clk clk~out0 mult242:inst40|Dout[14] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.099 ns" { clk dff89:inst34|Dout[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.099 ns" { clk clk~out0 dff89:inst34|Dout[0] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "add889:inst18\|Dout\[5\] Din\[4\] clk 5.016 ns register " "Info: tsu for register \"add889:inst18\|Dout\[5\]\" (data pin = \"Din\[4\]\", clock pin = \"clk\") is 5.016 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.126 ns + Longest pin register " "Info: + Longest pin to register delay is 7.126 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns Din\[4\] 1 PIN PIN_38 3 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_38; Fanout = 3; PIN Node = 'Din\[4\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[4] } "NODE_NAME" } } { "fir.bdf" "" { Schematic "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/fir.bdf" { { 120 -64 104 136 "Din\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.792 ns) + CELL(0.553 ns) 6.480 ns add889:inst18\|Dout\[4\]~40 2 COMB LC_X19_Y6_N4 4 " "Info: 2: + IC(4.792 ns) + CELL(0.553 ns) = 6.480 ns; Loc. = LC_X19_Y6_N4; Fanout = 4; COMB Node = 'add889:inst18\|Dout\[4\]~40'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.345 ns" { Din[4] add889:inst18|Dout[4]~40 } "NODE_NAME" } } { "add889.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/add889.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.646 ns) 7.126 ns add889:inst18\|Dout\[5\] 3 REG LC_X19_Y6_N5 5 " "Info: 3: + IC(0.000 ns) + CELL(0.646 ns) = 7.126 ns; Loc. = LC_X19_Y6_N5; Fanout = 5; REG Node = 'add889:inst18\|Dout\[5\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.646 ns" { add889:inst18|Dout[4]~40 add889:inst18|Dout[5] } "NODE_NAME" } } { "add889.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/add889.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.334 ns ( 32.75 % ) " "Info: Total cell delay = 2.334 ns ( 32.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.792 ns ( 67.25 % ) " "Info: Total interconnect delay = 4.792 ns ( 67.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.126 ns" { Din[4] add889:inst18|Dout[4]~40 add889:inst18|Dout[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.126 ns" { Din[4] Din[4]~out0 add889:inst18|Dout[4]~40 add889:inst18|Dout[5] } { 0.000ns 0.000ns 4.792ns 0.000ns } { 0.000ns 1.135ns 0.553ns 0.646ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "add889.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/add889.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.139 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 435 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 435; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fir.bdf" "" { Schematic "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns add889:inst18\|Dout\[5\] 2 REG LC_X19_Y6_N5 5 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X19_Y6_N5; Fanout = 5; REG Node = 'add889:inst18\|Dout\[5\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.009 ns" { clk add889:inst18|Dout[5] } "NODE_NAME" } } { "add889.vhd" "" { Text "C:/Documents and Settings/li/桌面/17阶FIR滤波器VHDL代码及说明文档/firOK/add889.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.40 % ) " "Info: Total cell delay = 1.677 ns ( 78.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.60 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk add889:inst18|Dout[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 add889:inst18|Dout[5] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.126 ns" { Din[4] add889:inst18|Dout[4]~40 add889:inst18|Dout[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.126 ns" { Din[4] Din[4]~out0 add889:inst18|Dout[4]~40 add889:inst18|Dout[5] } { 0.000ns 0.000ns 4.792ns 0.000ns } { 0.000ns 1.135ns 0.553ns 0.646ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk add889:inst18|Dout[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 add889:inst18|Dout[5] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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