mult18.vhd

17阶FIR滤波器VHDL代码及说明文档 下载立即可以仿真

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mult18 is
PORT
( clk :  IN STD_LOGIC;
  Din :  IN SIGNED (8 DOWNTO 0);
 Dout :  OUT SIGNED (12 DOWNTO 0));
END mult18;
ARCHITECTURE a OF mult18 IS
SIGNAL s1 : SIGNED (12 DOWNTO 0);
SIGNAL s2 : SIGNED (9 DOWNTO 0);
SIGNAL s3 : SIGNED (12 DOWNTO 0);


BEGIN
P1:process(Din)
BEGIN
s1(12 DOWNTO 4)<=Din;
s1( 3 DOWNTO 0)<="0000";
s2(9 DOWNTO 1)<=Din;
s2(0)<='0';
if Din(8)='0' then 
s3<=('0'&s1(12 downto 1))+("0000"&s2(9 DOWNTO 1));

else 
s3<=('1'&s1(12 downto 1))+("1111"&s2(9 DOWNTO 1));

end if;
end process;
P2: PROCESS(clk)
BEGIN
if clk'event and clk='1' then
Dout<=s3;
end if;
END PROCESS;
END a;