fir.map.rpt

17阶FIR滤波器VHDL代码及说明文档 下载立即可以仿真

Info: Found 2 design units, including 1 entities, in source file add121313.vhd
    Info: Found design unit 1: add121313-a
    Info: Found entity 1: add121313
Info: Found 2 design units, including 1 entities, in source file add121414.vhd
    Info: Found design unit 1: add121414-a
    Info: Found entity 1: add121414
Info: Found 2 design units, including 1 entities, in source file add121616.vhd
    Info: Found design unit 1: add121616-a
    Info: Found entity 1: add121616
Info: Found 2 design units, including 1 entities, in source file add141616.vhd
    Info: Found design unit 1: add141616-a
    Info: Found entity 1: add141616
Info: Found 2 design units, including 1 entities, in source file add889.vhd
    Info: Found design unit 1: add889-a
    Info: Found entity 1: add889
Info: Found 2 design units, including 1 entities, in source file dff8.vhd
    Info: Found design unit 1: dff8-a
    Info: Found entity 1: dff8
Info: Found 2 design units, including 1 entities, in source file mult12.vhd
    Info: Found design unit 1: mult12-a
    Info: Found entity 1: mult12
Info: Found 2 design units, including 1 entities, in source file mult13.vhd
    Info: Found design unit 1: mult13-a
    Info: Found entity 1: mult13
Info: Found 2 design units, including 1 entities, in source file mult14.vhd
    Info: Found design unit 1: mult14-a
    Info: Found entity 1: mult14
Info: Found 2 design units, including 1 entities, in source file mult162.vhd
    Info: Found design unit 1: mult162-a
    Info: Found entity 1: mult162
Info: Found 2 design units, including 1 entities, in source file mult18.vhd
    Info: Found design unit 1: mult18-a
    Info: Found entity 1: mult18
Info: Found 2 design units, including 1 entities, in source file mult242.vhd
    Info: Found design unit 1: mult242-a
    Info: Found entity 1: mult242
Info: Found 2 design units, including 1 entities, in source file mult29.vhd
    Info: Found design unit 1: mult29-a
    Info: Found entity 1: mult29
Info: Found 2 design units, including 1 entities, in source file sub131314.vhd
    Info: Found design unit 1: sub131314-a
    Info: Found entity 1: sub131314
Info: Found 2 design units, including 1 entities, in source file sub141616.vhd
    Info: Found design unit 1: sub141616-a
    Info: Found entity 1: sub141616
Info: Found 1 design units, including 1 entities, in source file fir.bdf
    Info: Found entity 1: fir
Info: Elaborating entity "fir" for the top level hierarchy
Info: Elaborating entity "add888" for hierarchy "add888:inst44"
Info: Elaborating entity "add141616" for hierarchy "add141616:inst39"
Info: Elaborating entity "sub131314" for hierarchy "sub131314:inst37"
Info: Elaborating entity "add121313" for hierarchy "add121313:inst"
Info: Elaborating entity "mult12" for hierarchy "mult12:inst26"
Warning (10492): VHDL Process Statement warning at mult12.vhd(23): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult12.vhd(23): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult12.vhd(26): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult12.vhd(26): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "add889" for hierarchy "add889:inst18"
Info: Elaborating entity "dff8" for hierarchy "dff8:inst17"
Info: Elaborating entity "mult18" for hierarchy "mult18:inst27"
Warning (10492): VHDL Process Statement warning at mult18.vhd(24): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult18.vhd(24): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult18.vhd(27): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult18.vhd(27): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "mult13" for hierarchy "mult13:inst28"
Warning (10492): VHDL Process Statement warning at mult13.vhd(24): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult13.vhd(24): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult13.vhd(27): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult13.vhd(27): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "mult29" for hierarchy "mult29:inst29"
Warning (10492): VHDL Process Statement warning at mult29.vhd(27): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult29.vhd(27): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult29.vhd(27): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult29.vhd(30): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult29.vhd(30): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult29.vhd(30): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "sub141616" for hierarchy "sub141616:inst38"
Info: Elaborating entity "add121414" for hierarchy "add121414:inst35"
Info: Elaborating entity "mult52" for hierarchy "mult52:inst31"
Warning (10492): VHDL Process Statement warning at mult52.vhd(27): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult52.vhd(27): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult52.vhd(27): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult52.vhd(30): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult52.vhd(30): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult52.vhd(30): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "add121616" for hierarchy "add121616:inst36"
Info: Elaborating entity "mult14" for hierarchy "mult14:inst32"
Warning (10492): VHDL Process Statement warning at mult14.vhd(26): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult14.vhd(26): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult14.vhd(26): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult14.vhd(29): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult14.vhd(29): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult14.vhd(29): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "mult162" for hierarchy "mult162:inst33"
Warning (10492): VHDL Process Statement warning at mult162.vhd(27): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult162.vhd(27): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult162.vhd(27): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult162.vhd(30): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult162.vhd(30): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult162.vhd(30): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "dff15" for hierarchy "dff15:inst43"
Info: Elaborating entity "mult242" for hierarchy "mult242:inst40"
Warning (10492): VHDL Process Statement warning at mult242.vhd(29): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult242.vhd(29): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult242.vhd(29): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult242.vhd(29): signal "s4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult242.vhd(32): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult242.vhd(32): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult242.vhd(32): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mult242.vhd(32): signal "s4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "dff89" for hierarchy "dff89:inst34"
Info: Duplicate registers merged to single register
    Info: Duplicate register "dff8:inst10|Dout[0]" merged to single register "dff89:inst34|Dout[0]"
    Info: Duplicate register "dff8:inst10|Dout[1]" merged to single register "dff89:inst34|Dout[1]"
    Info: Duplicate register "dff8:inst10|Dout[2]" merged to single register "dff89:inst34|Dout[2]"
    Info: Duplicate register "dff8:inst10|Dout[3]" merged to single register "dff89:inst34|Dout[3]"
    Info: Duplicate register "dff8:inst10|Dout[4]" merged to single register "dff89:inst34|Dout[4]"
    Info: Duplicate register "dff8:inst10|Dout[5]" merged to single register "dff89:inst34|Dout[5]"
    Info: Duplicate register "dff8:inst10|Dout[6]" merged to single register "dff89:inst34|Dout[6]"
    Info: Duplicate register "dff89:inst34|Dout[8]" merged to single register "dff89:inst34|Dout[7]"
    Info: Duplicate register "dff8:inst10|Dout[7]" merged to single register "dff89:inst34|Dout[7]"
Warning: Reduced register "mult162:inst33|Dout[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "mult52:inst31|Dout[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "mult12:inst26|Dout[0]" with stuck data_in port to stuck value GND
Info: Implemented 720 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 8 output pins
    Info: Implemented 702 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 47 warnings
    Info: Processing ended: Wed May 07 15:50:33 2008
    Info: Elapsed time: 00:00:26