portcout.v

Verilog语言描述的Intel8255 IP Core

               portcoutregd[3] = 1'b0 ; // Reset INTRA on read strobe
            end
            else if (risepcin4 == 1'b1 & (portcoutregq[5]) == 1'b1)
            begin
               portcoutregd[3] = portcoutregq[4] ; // Set INTRA on rising edge of STBA
            end
            else
            begin
               portcoutregd[3] = portcoutregq[3] ; 
            end 
         end 
      end
      else if ((modea[1]) == 1'b1)
      begin
         if ((portcoutld[3]) == 1'b0 & portcoverride == 1'b1)
         begin
            portcoutregd[3] = din[0] ; // Load from bit set/reset
         end
         else
         begin
            // Mode 2
            if (portawrite == 1'b0 | portaread == 1'b0)
            begin
               // Reset INTRA on either read or write strobes
               portcoutregd[3] = 1'b0 ; 
            end
            else if (portawrite == 1'b1 & risepcin6 == 1'b1 & (portcoutregq[7]) == 1'b1)
            begin
               // Set INTRA on rising edge of ACKA
               portcoutregd[3] = portcoutregq[6] ; 
            end
            else if (portaread == 1'b1 & risepcin4 == 1'b1 & (portcoutregq[5]) == 1'b1)
            begin
               // OR
               // Set INTRA on rising edge of STBA
               portcoutregd[3] = portcoutregq[4] ; 
            end
            else
            begin
               portcoutregd[3] = portcoutregq[3] ; 
            end 
         end 
      end
      else
      begin
         portcoutregd[3] = portcoutregq[3] ; 
      end 
   end

//==========Bit 4==================
   always @(modea or porta_io or portcoverride or  
            portcoutld or portcoutregq or din)
   begin
      if (modea == 2'b00 | (modea == 2'b01 & porta_io == 1'b0))
      begin
         if ((portcoutld[4]) == 1'b0)
         begin
            // Mode 0 and Mode 1 Output
            if (portcoverride == 1'b1)
            begin
               portcoutregd[4] = din[0] ; // Load INTEA from bit set/reset
            end
            else
            begin
               portcoutregd[4] = din[4] ; // Load INTEA from bus
            end 
         end
         else
         begin
            portcoutregd[4] = portcoutregq[4] ; 
         end // Mode 1 Input and Mode 2
      end
      else
      begin
         if ((portcoutld[4]) == 1'b0 & portcoverride == 1'b1)
         begin
            portcoutregd[4] = din[0] ; // Load INTEA(2) from bit set/reset
         end
         else
         begin
            portcoutregd[4] = portcoutregq[4] ; 
         end 
      end 
   end

//==========Bit 5==================
   always @(modea or porta_io or portcoverride or riseportaread or 
            portcoutld or portcoutregq or din or pcin)
   begin
      if (modea == 2'b00 | (modea == 2'b01 & porta_io == 1'b0))
      begin
         if ((portcoutld[5]) == 1'b0)
         begin
            // Mode 0 and Mode 1 Output
            if (portcoverride == 1'b1)
            begin
               portcoutregd[5] = din[0] ; // Load from bit set/reset
            end
            else
            begin
               portcoutregd[5] = din[5] ; // Load from bus
            end 
         end
         else
         begin
            portcoutregd[5] = portcoutregq[5] ; 
         end 
      end
      else if (modea == 2'b01)
      begin
         // Mode 1
         if ((portcoutld[5]) == 1'b0 & portcoverride == 1'b1)
         begin
            portcoutregd[5] = din[0] ; // Load from bit set/reset
         end
         else if (porta_io == 1'b1)
         begin
            // Mode 1 Input
            if (riseportaread == 1'b1 & (portcoutregq[3]) == 1'b0)
            begin
               portcoutregd[5] = 1'b0 ; // Reset IBFA on rising edge of read strobe
            end
            else if ((pcin[4]) == 1'b0)
            begin
               portcoutregd[5] = 1'b1 ; // Set IBFA when STBA goes low
            end
            else
            begin
               portcoutregd[5] = portcoutregq[5] ; 
            end 
         end
         else
         begin
            portcoutregd[5] = portcoutregq[5] ; 
         end 
      end
      else if ((modea[1]) == 1'b1)
      begin
         if ((portcoutld[5]) == 1'b0 & portcoverride == 1'b1)
         begin
            portcoutregd[5] = din[0] ; // Load from bit set/reset
         end
         else
         begin
            // Mode 2
            if (riseportaread == 1'b1 & (portcoutregq[3]) == 1'b0)
            begin
               portcoutregd[5] = 1'b0 ; // Reset IBFA on rising edge of read strobe
            end
            else if ((pcin[4]) == 1'b0)
            begin
               portcoutregd[5] = 1'b1 ; // Set IBFA when STBA goes low
            end
            else
            begin
               portcoutregd[5] = portcoutregq[5] ; 
            end 
         end 
      end
      else
      begin
         portcoutregd[5] = portcoutregq[5] ; 
      end 
   end

//==========Bit 6==================
   always @(modea or porta_io or portcoverride or 
            portcoutld or portcoutregq or din)
   begin
      if (modea == 2'b00 | (modea == 2'b01 & porta_io == 1'b1))
      begin
         if ((portcoutld[6]) == 1'b0)
         begin
            // Mode 0 and Mode 1 Input
            if (portcoverride == 1'b1)
            begin
               portcoutregd[6] = din[0] ; // Load INTEA from bit set/reset
            end
            else
            begin
               portcoutregd[6] = din[6] ; // Load INTEA from bus
            end 
         end
         else
         begin
            portcoutregd[6] = portcoutregq[6] ; 
         end 
      end
      else
      begin
         if ((portcoutld[6]) == 1'b0 & portcoverride == 1'b1)
         begin
            portcoutregd[6] = din[0] ; // Load INTEA(1) from bit set/reset
         end
         else
         begin
            portcoutregd[6] = portcoutregq[6] ; 
         end 
      end 
   end

//==========Bit 7==================
   always @(modea or porta_io or portcoverride or riseportawrite or
            portcoutld or portcoutregq or din or pcin)
   begin
      if (modea == 2'b00 | (modea == 2'b01 & porta_io == 1'b1))
      begin
         if ((portcoutld[7]) == 1'b0)
         begin
            // Mode 0 and Mode 1 Input
            if (portcoverride == 1'b1)
            begin
               portcoutregd[7] = din[0] ; // Load from bit set/reset
            end
            else
            begin
               portcoutregd[7] = din[7] ; // Load from bus
            end 
         end
         else
         begin
            portcoutregd[7] = portcoutregq[7] ; 
         end 
      end
      else if (modea == 2'b01)
      begin
         // Mode 1
         if ((portcoutld[7]) == 1'b0 & portcoverride == 1'b1)
         begin
            portcoutregd[7] = din[0] ; 
         end
         else if (porta_io == 1'b0)
         begin
            // Mode 1 Output
            if (riseportawrite == 1'b1)
            begin
               portcoutregd[7] = 1'b0 ; // Reset OBFA on rising edge of Write strobe
            end
            else if ((pcin[6]) == 1'b0)
            begin
               portcoutregd[7] = 1'b1 ; // Set OBFA when ACKA goes low
            end
            else
            begin
               portcoutregd[7] = portcoutregq[7] ; 
            end 
         end
         else
         begin
            portcoutregd[7] = portcoutregq[7] ; 
         end 
      end
      else if ((modea[1]) == 1'b1)
      begin
         if ((portcoutld[7]) == 1'b0 & portcoverride == 1'b1)
         begin
            portcoutregd[7] = din[0] ; // Load from bit set/reset
         end
         else
         begin
            // Mode 2
            if (riseportawrite == 1'b1)
            begin
               // Reset OBFA on rising edge of write strobe
               portcoutregd[7] = 1'b0 ; 
            end
            else if ((pcin[6]) == 1'b0)
            begin
               // Set OBFA when ACKA goes low
               portcoutregd[7] = 1'b1 ; 
            end
            else
            begin
               portcoutregd[7] = portcoutregq[7] ; 
            end 
         end 
      end
      else
      begin
         portcoutregd[7] = portcoutregq[7] ; 
      end 
   end 

   // Process for Port C output register
   always @(posedge reset or posedge clk)
   begin : portcoutregsyncproc
      if (reset == 1'b1)
      begin
         portcoutregq <= 8'b00000000 ; 
      end
      else
      begin
         portcoutregq <= portcoutregd ; 
      end 
   end 

   // Process for edge detect registers
   always @(posedge reset or posedge clk)
   begin : edgedetectsyncproc
      if (reset == 1'b1)
      begin
         riseportawriteq <= 1'b0 ; 
         riseportbwriteq <= 1'b0 ; 
         riseportareadq <= 1'b0 ; 
         riseportbreadq <= 1'b0 ; 
         risepcin6q <= 1'b0 ; 
         risepcin4q <= 1'b0 ; 
         risepcin2q <= 1'b0 ; 
      end
      else
      begin
         riseportawriteq <= portawrite ; 
         riseportbwriteq <= portbwrite ; 
         riseportareadq <= portaread ; 
         riseportbreadq <= portbread ; 
         risepcin6q <= pcin[6] ; 
         risepcin4q <= pcin[4] ; 
         risepcin2q <= pcin[2] ; 
      end 
   end 
   // Assignments for edge detect signals
   assign riseportawrite = portawrite & ~riseportawriteq ;
   assign riseportbwrite = portbwrite & ~riseportbwriteq ;
   assign riseportaread = portaread & ~riseportareadq ;
   assign riseportbread = portbread & ~riseportbreadq ;
   assign risepcin6 = pcin[6] & ~risepcin6q ;
   assign risepcin4 = pcin[4] & ~risepcin4q ;
   assign risepcin2 = pcin[2] & ~risepcin2q ;
endmodule