portcout.v

Verilog语言描述的Intel8255 IP Core

`timescale 1ns /10ps
module portcout (reset, clk, din, pcin, controlreg, portaread, portbread, portawrite, portbwrite, portcoverride, portcoutld, portcstatus, pcout);

   input reset; 
   input clk; 
   input[7:0] din; 
   input[7:0] pcin; 
   input[7:0] controlreg; 
   input portaread; 
   input portbread; 
   input portawrite; 
   input portbwrite; 
   input portcoverride; 
   input[7:0] portcoutld; 
   output[7:0] portcstatus; 
   reg[7:0] portcstatus;
   output[7:0] pcout; 
   wire[7:0] pcout;

   reg[7:0] portcoutregd; 
   reg[7:0] portcoutregq; 
   wire[1:0] modea; 
   wire modeb; 
   wire porta_io; 
   wire portb_io; 
   reg riseportawriteq; 
   reg riseportbwriteq; 
   reg riseportareadq; 
   reg riseportbreadq; 
   reg risepcin6q; 
   reg risepcin4q; 
   reg risepcin2q; 
   wire riseportawrite; 
   wire riseportbwrite; 
   wire riseportaread; 
   wire riseportbread; 
   wire risepcin6; 
   wire risepcin4; 
   wire risepcin2; 

   assign pcout = portcoutregq ;
   assign modea = controlreg[6:5] ;
   assign modeb = controlreg[2] ;
   assign porta_io = controlreg[4] ;
   assign portb_io = controlreg[1] ;

//==========Bit 7==================
   always @(pcin)
   begin
      portcstatus[7] = pcin[7] ; 
   end
//==========Bit 6==================
   always @(modea or porta_io or pcin or portcoutregq)
   begin
      if (modea == 2'b01 & porta_io == 1'b0)
      begin
         // Mode 1
         portcstatus[6] = portcoutregq[6] ; 
      end
      else if ((modea[1]) == 1'b1)
      begin
         // Mode 2
         portcstatus[6] = portcoutregq[6] ; 
      end
      else
      begin
         portcstatus[6] = pcin[6] ; 
      end 
   end
//==========Bit 5==================
   always @(pcin)
   begin
      portcstatus[5] = pcin[5] ; 
   end
//==========Bit 4==================
   always @(modea or porta_io or pcin or portcoutregq)
   begin
      if (modea == 2'b01 & porta_io == 1'b1)
      begin
         // Mode 1
         portcstatus[4] = portcoutregq[4] ; 
      end
      else if ((modea[1]) == 1'b1)
      begin
         // Mode 2
         portcstatus[4] = portcoutregq[4] ; 
      end
      else
      begin
         portcstatus[4] = pcin[4] ; 
      end 
   end
//==========Bit 3==================
   always @(pcin)
   begin
      portcstatus[3] = pcin[3] ; 
   end
//==========Bit 2==================
   always @(modeb or pcin or portcoutregq)
   begin
      if (modeb == 1'b1)
      begin
         // Mode 1
         portcstatus[2] = portcoutregq[2] ; 
      end
      else
      begin
         portcstatus[2] = pcin[2] ; 
      end 
   end
//==========Bit 1:0==================
   always @(pcin)
   begin
      portcstatus[1] = pcin[1] ; 
      portcstatus[0] = pcin[0] ; 
   end

//==========Bit 0==================
   always @(portb_io or modeb or portcoverride or portbwrite or portbread
            or portcoutld or portcoutregq or din or risepcin2)
   begin
      if (modeb == 1'b0)
      begin
         // Mode 0
         if ((portcoutld[0]) == 1'b0)
         begin
            // Load from bus and bit set/reset
            portcoutregd[0] = din[0] ; 
         end
         else
         begin
            portcoutregd[0] = portcoutregq[0] ; 
         end 
      end
      else if (modeb == 1'b1)
      begin
         if ((portcoutld[0]) == 1'b0 & portcoverride == 1'b1)
         begin
            // Load for the set/reset command
            portcoutregd[0] = din[0] ; // Mode 1 Output
         end
         else if (portb_io == 1'b0)
         begin
            // Mode 1
            if (portbwrite == 1'b0)
            begin
               // Reset INTRB on write strobe
               portcoutregd[0] = 1'b0 ; 
            end
            else if (portbwrite == 1'b1 & risepcin2 == 1'b1 & (portcoutregq[1]) == 1'b1)
            begin
               // Set INTRB on rising edge of ACKB
               portcoutregd[0] = portcoutregq[2] ; 
            end
            else
            begin
               portcoutregd[0] = portcoutregq[0] ; 
            end 
         end
         else
         begin
            // Mode 1 Input
            if (portbread == 1'b0 & (portcoutregq[1]) == 1'b1)
            begin
               // Reset INTRB on read strobe
               portcoutregd[0] = 1'b0 ; 
            end
            else if (risepcin2 == 1'b1 & (portcoutregq[1]) == 1'b1)
            begin
               // Set INTRB on rising edge of STBB
               portcoutregd[0] = portcoutregq[2] ; 
            end
            else
            begin
               portcoutregd[0] = portcoutregq[0] ; 
            end 
         end 
      end
      else
      begin
         portcoutregd[0] = portcoutregq[0] ; 
      end 
   end

//==========Bit 1==================
   always @(portb_io or modeb or portcoverride or riseportbwrite or 
            riseportbread or portcoutld or portcoutregq or din or pcin)
   begin
      if (modeb == 1'b0)
      begin
         if ((portcoutld[1]) == 1'b0)
         begin
            // Mode 0
            if (portcoverride == 1'b1)
            begin
               portcoutregd[1] = din[0] ; // Load from bit set/reset
            end
            else
            begin
               portcoutregd[1] = din[1] ; // Load from bus
            end 
         end
         else
         begin
            portcoutregd[1] = portcoutregq[1] ; 
         end 
      end
      else if (modeb == 1'b1)
      begin
         // Mode 1
         if ((portcoutld[1]) == 1'b0 & portcoverride == 1'b1)
         begin
            // Load from bit set/reset
            portcoutregd[1] = din[0] ; 
         end
         else if (portb_io == 1'b0)
         begin
            // Mode 1 Output
            if (riseportbwrite == 1'b1)
            begin
               // Reset OBFB on rising edge of write strobe
               portcoutregd[1] = 1'b0 ; 
            end
            else if ((pcin[2]) == 1'b0)
            begin
               // Set OBFB when ACKB goes low
               portcoutregd[1] = 1'b1 ; 
            end
            else
            begin
               portcoutregd[1] = portcoutregq[1] ; 
            end 
         end
         else
         begin
            // Mode 1 Input
            if (riseportbread == 1'b1 & (portcoutregq[0]) == 1'b0)
            begin
               // Reset IBFB on rising edge of read strobe
               portcoutregd[1] = 1'b0 ; 
            end
            else if ((pcin[2]) == 1'b0)
            begin
               // Set IBFB when STBB goes low
               portcoutregd[1] = 1'b1 ; 
            end
            else
            begin
               portcoutregd[1] = portcoutregq[1] ; 
            end 
         end 
      end
      else
      begin
         portcoutregd[1] = portcoutregq[1] ; 
      end
   end

//==========Bit 2==================
   always @(portcoverride or portcoutld or portcoutregq or din)
   begin
      if ((portcoutld[2]) == 1'b0)
      begin
         // All Modes
         if (portcoverride == 1'b1)
         begin
            portcoutregd[2] = din[0] ; // Load INTEB from bit set/reset
         end
         else
         begin
            portcoutregd[2] = din[2] ; // Load INTEB from bus
         end 
      end
      else
      begin
         portcoutregd[2] = portcoutregq[2] ; 
      end 
   end

//==========Bit 3==================
   always @(modea or porta_io or portcoverride or portawrite or 
            portaread or portcoutld or portcoutregq or din or risepcin4 or risepcin6)
   begin
      if (modea == 2'b00)
      begin
         if ((portcoutld[3]) == 1'b0)
         begin
            // Mode 0
            if (portcoverride == 1'b1)
            begin
               portcoutregd[3] = din[0] ; // Load from bit set/reset
            end
            else
            begin
               portcoutregd[3] = din[3] ; // Load from bus
            end 
         end
         else
         begin
            portcoutregd[3] = portcoutregq[3] ; 
         end 
      end
      else if (modea == 2'b01)
      begin
         // Mode 1
         if ((portcoutld[3]) == 1'b0 & portcoverride == 1'b1)
         begin
            portcoutregd[3] = din[0] ; // Load from bit set/reset
         end
         else if (porta_io == 1'b0)
         begin
            // Mode 1 Output
            if (portawrite == 1'b0)
            begin
               portcoutregd[3] = 1'b0 ; // Reset INTRA on write strobe
            end
            else if (portawrite == 1'b1 & risepcin6 == 1'b1 & (portcoutregq[7]) == 1'b1)
            begin
               // Set INTRA on rising edge of ACKA
               portcoutregd[3] = portcoutregq[6] ; 
            end
            else
            begin
               portcoutregd[3] = portcoutregq[3] ; 
            end 
         end
         else
         begin
            // Mode 1 Input
            if (portaread == 1'b0 & (portcoutregq[5]) == 1'b1)
            begin