📄 cntl_log.v
字号:
`timescale 1ns /10ps
module cntl_log (reset, clk, ncs, nrd, nwr, a, din, pcin, paen, pben, pcen, doutselect, controlreg, portaread, portbread, portawrite, portbwrite, portaoutld, portboutld, portcoverride, portcoutld);
input reset;
input clk;
input ncs;
input nrd;
input nwr;
input[1:0] a;
input[7:0] din;
input[7:0] pcin;
output paen;
reg paen;
output pben;
reg pben;
output[7:0] pcen;
reg[7:0] pcen;
output[2:0] doutselect;
reg[2:0] doutselect;
output[7:0] controlreg;
wire[7:0] controlreg;
output portaread;
wire portaread;
output portbread;
wire portbread;
output portawrite;
wire portawrite;
output portbwrite;
wire portbwrite;
output portaoutld;
wire portaoutld;
output portboutld;
wire portboutld;
output portcoverride;
reg portcoverride;
output[7:0] portcoutld;
wire[7:0] portcoutld;
reg[6:0] controlregd;
reg[6:0] controlregq;
reg[7:0] portcoutld_bit;
reg[7:0] portcoutld_byte;
wire[1:0] modea;
wire modeb;
wire porta_io;
wire portb_io;
wire portcup_io;
wire portclow_io;
wire controlregwrite;
assign controlreg = {1'b1, controlregq} ;
assign modea = controlregq[6:5] ;
assign modeb = controlregq[2] ;
assign porta_io = controlregq[4] ;
assign portb_io = controlregq[1] ;
assign portcup_io = controlregq[3] ;
assign portclow_io = controlregq[0] ;
assign portaoutld = (ncs == 1'b0 & a == 2'b00 & nwr == 1'b0) ? 1'b0 : 1'b1 ;
assign portboutld = (ncs == 1'b0 & a == 2'b01 & nwr == 1'b0) ? 1'b0 : 1'b1 ;
assign portaread = ncs | nrd | a[1] | a[0] ;
assign portbread = ncs | nrd | a[1] | (~a[0]) ;
assign portawrite = ncs | nwr | a[1] | a[0] ;
assign portbwrite = ncs | nwr | a[1] | (~a[0]) ;
assign controlregwrite = ncs | nwr | (~a[1]) | (~a[0]) | (~din[7]) ;
always @(portb_io)
begin
pben = ~portb_io ;
end
always @(modea or modeb or portclow_io)
begin
if (modeb == 1'b0)
begin
if ((modea[1]) == 1'b1)
begin
pcen[3:0] = {1'b1, ~portclow_io, ~portclow_io, ~portclow_io} ;
end
else
begin
pcen[3:0] = {~portclow_io, ~portclow_io, ~portclow_io, ~portclow_io} ;
end
end
else
begin
pcen[3:0] = 4'b1011 ;
end
end
always @(modea or porta_io or pcin)
begin
if (modea == 2'b00)
begin
paen = ~porta_io ;
end
else if (modea == 2'b01)
begin
paen = ~porta_io ;
end
else
begin
paen = ~pcin[6] ; // ACK signal drives enable in Mode 2
end
end
always @(modea or portcup_io or porta_io)
begin
if (modea == 2'b00)
begin
pcen[7:4] = {~portcup_io, ~portcup_io, ~portcup_io, ~portcup_io} ;
end
else if (modea == 2'b01)
begin
if (porta_io == 1'b0)
begin
//Port A Output
pcen[7:4] = {2'b10, ~portcup_io, ~portcup_io} ;
end
else
begin
//Port A Input
pcen[7:4] = {~portcup_io, ~portcup_io, 2'b10} ;
end
end
else
begin
pcen[7:4] = 4'b1010 ;
end
end
always @(a or modea or modeb)
begin
case (a)
2'b00 :
begin
// Port A Data
if (modea == 2'b00)
begin
// If Port A is in Mode 0
doutselect = 3'b000 ; // then select unlatched PAIN data
end
else
begin
doutselect = 3'b001 ; // else select latched PAIN data
end
end
2'b01 :
begin
// Port B Data
if (modeb == 1'b0)
begin
// If Port B is in Mode 0
doutselect = 3'b010 ; // then select unlatched PBIN data
end
else
begin
doutselect = 3'b011 ; // else select latched PBIN data
end
end
2'b10 :
begin
// Port C Data
doutselect = 3'b100 ; // Select PCIN data
end
2'b11 :
begin
doutselect = 3'b110 ; // Select Control Register Data
end
default :
begin
end
endcase
end
always @(ncs or a or din)
begin
if (ncs == 1'b0 & a == 2'b11 & (din[7]) == 1'b0)
begin
portcoverride = 1'b1 ;
end
else
begin
portcoverride = 1'b0 ;
end
end
assign portcoutld= portcoutld_bit & portcoutld_byte;
always @(ncs or nwr or a or din or modea or modeb)
begin
if (ncs == 1'b0 )
begin
if(a == 2'b10)
begin
if(nwr == 1'b0)
begin
if (modea == 2'b00 & modeb == 1'b0)
begin
portcoutld_byte = 8'b00000000 ;
end
else if (modea == 2'b00)
begin
portcoutld_byte = 8'b00001111 ;
end
else if (modeb == 1'b0)
begin
portcoutld_byte = 8'b11110000 ;
end
else
begin
portcoutld_byte = 8'b11111111 ;
end
end
else
portcoutld_byte = 8'b11111111 ;
end
else
portcoutld_byte = 8'b11111111 ;
end
else
portcoutld_byte = 8'b11111111 ;
end
always @(ncs or nwr or a or din or modea or modeb)
begin
if (ncs == 1'b0 )
begin
if(a == 2'b11)
begin
if((din[7]) == 1'b0)
begin
if(nwr == 1'b0)
begin
case (din[3:1])
3'b000 :
begin
portcoutld_bit = 8'b11111110 ;
end
3'b001 :
begin
portcoutld_bit = 8'b11111101 ;
end
3'b010 :
begin
portcoutld_bit = 8'b11111011 ;
end
3'b011 :
begin
portcoutld_bit = 8'b11110111 ;
end
3'b100 :
begin
portcoutld_bit = 8'b11101111 ;
end
3'b101 :
begin
portcoutld_bit = 8'b11011111 ;
end
3'b110 :
begin
portcoutld_bit = 8'b10111111 ;
end
3'b111 :
begin
portcoutld_bit = 8'b01111111 ;
end
default :
begin
portcoutld_bit = 8'b11111111 ;
end
endcase
end
else
portcoutld_bit = 8'b11111111 ;
end
else
portcoutld_bit = 8'b11111111 ;
end
else
portcoutld_bit = 8'b11111111 ;
end
else
portcoutld_bit = 8'b11111111 ;
end
always @(din or controlregwrite or controlregq)
begin
if (controlregwrite == 1'b0)
begin
controlregd = din[6:0] ;
end
else
begin
controlregd = controlregq ;
end
end
always @(posedge reset or posedge clk)
begin : controlregproc
if (reset == 1'b1)
begin
controlregq <= 7'b0011011 ;
end
else
begin
controlregq <= controlregd ;
end
end
endmodule
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -