a8255.v

Verilog语言描述的Intel8255 IP Core

`timescale 1ns /10ps
module a8255 (reset, clk, ncs, nrd, nwr, a, din, pain, pbin, pcin, dout, paout, paen, pbout, pben, pcout, pcen);

   input reset; 
   input clk; 
   input ncs; 
   input nrd; 
   input nwr; 
   input[1:0] a; 
   input[7:0] din; 
   input[7:0] pain; 
   input[7:0] pbin; 
   input[7:0] pcin; 
   output[7:0] dout; 
   wire[7:0] dout;
   output[7:0] paout; 
   wire[7:0] paout;
   output paen; 
   wire paen;
   output[7:0] pbout; 
   wire[7:0] pbout;
   output pben; 
   wire pben;
   output[7:0] pcout; 
   wire[7:0] pcout;
   output[7:0] pcen; 
   wire[7:0] pcen;

   // SIGNAL DECLARATIONS
   wire[2:0] doutselect; 
   wire[7:0] controlreg; 
   wire portaoutld; 
   wire portboutld; 
   wire portcoverride; 
   wire[7:0] portcoutld; 
   wire[7:0] portainreg; 
   wire[7:0] portbinreg; 
   wire portaread; 
   wire portbread; 
   wire portawrite; 
   wire portbwrite; 
   wire[7:0] portcstatus; 
   wire[7:0] compositeportcstatus; 

   // COMPONENT_DECLARATIONS
   // CONCURRENT SIGNAL ASSIGNMENTS
   assign compositeportcstatus = {pcin[7], portcstatus[6], pcin[5], portcstatus[4], pcin[3], portcstatus[2], pcin[1], pcin[0]} ;
   // COMPONENT INSTANTIATIONS
   dout_mux i_dout_mux (
      .doutselect(doutselect), 
      .controlreg(controlreg), 
      .portainreg(portainreg), 
      .pain(pain), 
      .portbinreg(portbinreg), 
      .pbin(pbin), 
      .portcstatus(compositeportcstatus), 
      .dout(dout)
   ); 
   cntl_log i_cntl_log (
      .reset(reset), 
      .clk(clk), 
      .ncs(ncs), 
      .nrd(nrd), 
      .nwr(nwr), 
      .a(a), 
      .din(din), 
      .pcin(pcin), 
      .paen(paen), 
      .pben(pben), 
      .pcen(pcen), 
      .doutselect(doutselect), 
      .controlreg(controlreg), 
      .portaread(portaread), 
      .portbread(portbread), 
      .portawrite(portawrite), 
      .portbwrite(portbwrite), 
      .portaoutld(portaoutld), 
      .portboutld(portboutld), 
      .portcoverride(portcoverride), 
      .portcoutld(portcoutld)
   ); 
   portaout i_portaout (
      .din(din), 
      .reset(reset), 
      .clk(clk), 
      .portaoutld(portaoutld), 
      .paout(paout)
   ); 
   portain i_portain (
      .pain(pain), 
      .reset(reset), 
      .clk(clk), 
      .portainld(pcin[4]), 
      .portainreg(portainreg)
   ); 
   portbout i_portbout (
      .din(din), 
      .reset(reset), 
      .clk(clk), 
      .portboutld(portboutld), 
      .pbout(pbout)
   ); 
   portbin i_portbin (
      .pbin(pbin), 
      .reset(reset), 
      .clk(clk), 
      .portbinld(pcin[2]), 
      .portbinreg(portbinreg)
   ); 
   portcout i_portcout (
      .reset(reset), 
      .clk(clk), 
      .din(din), 
      .pcin(pcin), 
      .controlreg(controlreg), 
      .portaread(portaread), 
      .portbread(portbread), 
      .portawrite(portawrite), 
      .portbwrite(portbwrite), 
      .portcoutld(portcoutld), 
      .portcoverride(portcoverride), 
      .portcstatus(portcstatus), 
      .pcout(pcout)
   ); 
endmodule