main.map.rpt

VHDL实现的交通灯程序

; Name              ; temp_color~33 ; temp_color~32 ;
+-------------------+---------------+---------------+
; temp_color.green  ; 0             ; 0             ;
; temp_color.yellow ; 0             ; 1             ;
; temp_color.red    ; 1             ; 0             ;
; temp_color.turn   ; 1             ; 1             ;
+-------------------+---------------+---------------+


+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                    ;
+----------------------------+------------+------+-----------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name   ;
+----------------------------+------------+------+-----------------------+
; |Main                      ; 111        ; 24   ; |Main                 ;
;    |ControlA:u4|           ; 17         ; 0    ; |Main|ControlA:u4     ;
;    |ControlB:u5|           ; 15         ; 0    ; |Main|ControlB:u5     ;
;    |Debounce:u3|           ; 2          ; 0    ; |Main|Debounce:u3     ;
;    |Display:u8|            ; 21         ; 0    ; |Main|Display:u8      ;
;    |Emergency:u2|          ; 1          ; 0    ; |Main|Emergency:u2    ;
;    |Frequency1:u1|         ; 22         ; 0    ; |Main|Frequency1:u1   ;
;    |StatusSelect:u6|       ; 27         ; 0    ; |Main|StatusSelect:u6 ;
;    |TimeSelect:u7|         ; 4          ; 0    ; |Main|TimeSelect:u7   ;
+----------------------------+------------+------+-----------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/film/04112 刘巍 交通灯/6v/Main.map.eqn.


+------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                               ;
+------------------------------------------------------------------------------------+-----------------+
; File Name                                                                          ; Used in Netlist ;
+------------------------------------------------------------------------------------+-----------------+
; ControlA.vhd                                                                       ; yes             ;
; ControlB.vhd                                                                       ; yes             ;
; Debounce.vhd                                                                       ; yes             ;
; Display.vhd                                                                        ; yes             ;
; Emergency.vhd                                                                      ; yes             ;
; Frequency1.vhd                                                                     ; yes             ;
; StatusSelect.vhd                                                                   ; yes             ;
; TimeSelect.vhd                                                                     ; yes             ;
; Main.vhd                                                                           ; yes             ;
; d:/foreign/quartus4[1].1m/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf ; yes             ;
; d:/foreign/quartus4[1].1m/altera/quartus41/libraries/megafunctions/addcore.inc     ; yes             ;
; d:/foreign/quartus4[1].1m/altera/quartus41/libraries/megafunctions/look_add.inc    ; yes             ;
; d:/foreign/quartus4[1].1m/altera/quartus41/libraries/megafunctions/addcore.tdf     ; yes             ;
; d:/foreign/quartus4[1].1m/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf ; yes             ;
; d:/foreign/quartus4[1].1m/altera/quartus41/libraries/megafunctions/look_add.tdf    ; yes             ;
; d:/foreign/quartus4[1].1m/altera/quartus41/libraries/megafunctions/altshift.tdf    ; yes             ;
+------------------------------------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 111                  ;
; Total registers      ; 78                   ;
; I/O pins             ; 24                   ;
; Shareable expanders  ; 18                   ;
; Parallel expanders   ; 16                   ;
; Maximum fan-out node ; Emergency:u2|temp    ;
; Maximum fan-out      ; 57                   ;
; Total fan-out        ; 1346                 ;
; Average fan-out      ; 8.80                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Thu Nov 01 00:13:42 2007
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Main -c Main
Info: Found 2 design units, including 1 entities, in source file ControlA.vhd
    Info: Found design unit 1: ControlA-ControlA_arc
    Info: Found entity 1: ControlA
Info: Found 2 design units, including 1 entities, in source file ControlB.vhd
    Info: Found design unit 1: ControlB-ControlB_arc
    Info: Found entity 1: ControlB
Info: Found 2 design units, including 1 entities, in source file Debounce.vhd
    Info: Found design unit 1: Debounce-Debounce_arc
    Info: Found entity 1: Debounce
Info: Found 2 design units, including 1 entities, in source file Display.vhd
    Info: Found design unit 1: Display-Display_arc
    Info: Found entity 1: Display
Info: Found 2 design units, including 1 entities, in source file Emergency.vhd
    Info: Found design unit 1: Emergency-Emergency_arc
    Info: Found entity 1: Emergency
Info: Found 2 design units, including 1 entities, in source file Frequency1.vhd
    Info: Found design unit 1: Frequency1-Frequency1_arc
    Info: Found entity 1: Frequency1
Info: Found 2 design units, including 1 entities, in source file StatusSelect.vhd
    Info: Found design unit 1: StatusSelect-StatusSelect_arc
    Info: Found entity 1: StatusSelect
Info: Found 2 design units, including 1 entities, in source file TimeSelect.vhd
    Info: Found design unit 1: TimeSelect-TimeSelect_arc
    Info: Found entity 1: TimeSelect
Info: Found 2 design units, including 1 entities, in source file Main.vhd
    Info: Found design unit 1: Main-Main_arc
    Info: Found entity 1: Main
Warning: VHDL Variable Declaration warning at ControlA.vhd(18): ignored initial value expression for variable reset
Warning: VHDL Variable Declaration warning at ControlA.vhd(21): ignored initial value expression for variable temp_color
Warning: VHDL Variable Declaration warning at ControlB.vhd(18): ignored initial value expression for variable reset
Warning: VHDL Variable Declaration warning at ControlB.vhd(21): ignored initial value expression for variable temp_color
Warning: VHDL Process Statement warning at StatusSelect.vhd(54): signal temp is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at TimeSelect.vhd(18): signal timeh1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at TimeSelect.vhd(20): signal timel1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at TimeSelect.vhd(22): signal timeh2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at TimeSelect.vhd(24): signal timel2 is in statement, but is not in sensitivity list
Info: Found 1 design units, including 1 entities, in source file ../../../foreign/quartus4[1].1m/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file ../../../foreign/quartus4[1].1m/altera/quartus41/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file ../../../foreign/quartus4[1].1m/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file ../../../foreign/quartus4[1].1m/altera/quartus41/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file ../../../foreign/quartus4[1].1m/altera/quartus41/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: State machine |Main|ControlB:u5|temp_color contains 4 states and 0 state bits
Info: State machine |Main|ControlA:u4|temp_color contains 4 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine |Main|ControlB:u5|temp_color
Info: Encoding result for state machine |Main|ControlB:u5|temp_color
    Info: Completed encoding using 2 state bits
        Info: Encoded state bit ControlB:u5|temp_color~33
        Info: Encoded state bit ControlB:u5|temp_color~32
    Info: State |Main|ControlB:u5|temp_color.red uses code string 00
    Info: State |Main|ControlB:u5|temp_color.green uses code string 01
    Info: State |Main|ControlB:u5|temp_color.yellow uses code string 10
    Info: State |Main|ControlB:u5|temp_color.turn uses code string 11
Info: Selected Auto state machine encoding method for state machine |Main|ControlA:u4|temp_color
Info: Encoding result for state machine |Main|ControlA:u4|temp_color
    Info: Completed encoding using 2 state bits
        Info: Encoded state bit ControlA:u4|temp_color~33
        Info: Encoded state bit ControlA:u4|temp_color~32
    Info: State |Main|ControlA:u4|temp_color.green uses code string 00
    Info: State |Main|ControlA:u4|temp_color.yellow uses code string 01
    Info: State |Main|ControlA:u4|temp_color.red uses code string 10
    Info: State |Main|ControlA:u4|temp_color.turn uses code string 11
Warning: Output pins are stuck at VCC or GND
    Warning: Pin catn[3] stuck at VCC
    Warning: Pin catn[2] stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin clk to global clock signal
Info: Implemented 153 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 22 output pins
    Info: Implemented 111 macrocells
    Info: Implemented 18 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Processing ended: Thu Nov 01 00:14:03 2007
    Info: Elapsed time: 00:00:21