frequency1.vhd

来自「VHDL实现的交通灯程序」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Frequency1 is
	port(
		clk:in std_logic;
		clk_out:out std_logic
		);
end Frequency1;

architecture Frequency1_arc of Frequency1 is
begin
	process(clk)
	variable temp:integer range 0 to 999999;
	begin
		if(clk'event and clk='1')then
			if(temp=999999)then
				temp:=0;
				clk_out<='0';
			else
				temp:=temp+1;
				clk_out<='1';
			end if;
		end if;
	end process;
end;