📄 main.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity Main is
port(
clk,key:in std_logic;
r1,g1,y1,r2,g2,y2,t1,t2:out std_logic;
voice:out std_logic;
num:out std_logic_vector(6 downto 0);
catn:out std_logic_vector(5 downto 0)
);
end Main;
architecture Main_arc of Main is
signal temp_clk, temp_key, temp_show: std_logic;
signal temp_sel: std_logic_vector(2 downto 0);
signal temph1,temph2,templ1,templ2,tempout: std_logic_vector(3 downto 0);
component Debounce is
port(
key,clk: in std_logic;
key_out: out std_logic
);
end component;
component Emergency is
port(
BTN_in:in std_logic;
BTN_out:out std_logic
);
end component;
component Frequency1 is
port(
clk:in std_logic;
clk_out:out std_logic
);
end component;
component StatusSelect is
port(
clk,show:in std_logic;
sel:out std_logic_vector(2 downto 0);
voice:out std_logic
);
end component;
component TimeSelect is
port(
sel:in std_logic_vector(2 downto 0);
timeh1,timeh2,timel1,timel2 :in std_logic_vector(3 downto 0);
catn:out std_logic_vector(5 downto 0);
time_out:out std_logic_vector(3 downto 0)
);
end component;
component ControlA is
port(
clk,show:in std_logic;
timeh,timel:out std_logic_vector(3 downto 0);
r,g,y,t:out std_logic
);
end component;
component ControlB is
port(
clk,show:in std_logic;
timeh,timel:out std_logic_vector(3 downto 0);
r,g,y,t:out std_logic
);
end component;
component Display is
port(
num_in:in std_logic_vector(3 downto 0);
num_out:out std_logic_vector(6 downto 0)
);
end component;
begin
u1:Frequency1 port map(clk=>clk, clk_out=>temp_clk);
u2:Emergency port map(BTN_in=>temp_key, BTN_out=>temp_show);
u3:Debounce port map(clk=>temp_clk, key=>key, key_out=>temp_key);
u4:ControlA port map(clk=>temp_clk, show=>temp_show, r=>r1, g=>g1, y=>y1,t=>t1,
timeh=>temph1, timel=>templ1);
u5:ControlB port map(clk=>temp_clk, show=>temp_show, r=>r2, g=>g2, y=>y2,t=>t2,
timeh=>temph2, timel=>templ2);
u6:StatusSelect port map(clk=>clk, show=>temp_show, sel=>temp_sel,voice=>voice);
u7:TimeSelect port map(sel=>temp_sel, timeh1=>temph1, timel1=>templ1,timeh2=>temph2, timel2=>templ2, catn=>catn, time_out=>tempout);
u8:Display port map(num_in=>tempout, num_out=>num);
end;
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