📄 timeselect.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity TimeSelect is
port(
sel:in std_logic_vector(2 downto 0);
timeh1,timeh2,timel1,timel2:in std_logic_vector(3 downto 0);
catn:out std_logic_vector(5 downto 0);
time_out:out std_logic_vector(3 downto 0)
);
end TimeSelect;
architecture TimeSelect_arc of TimeSelect is
begin
process(sel)
begin
case sel is
when "000"=>time_out<=timeh1;
catn<="111110";
when "001"=>time_out<=timel1;
catn<="111101";
when "010"=>time_out<=timeh2;
catn<="101111";
when "011"=>time_out<=timel2;
catn<="011111";
when others=>time_out<="0000";
catn<="111111";
end case;
end process;
end;
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