vgaps2.fit.smsg

用VHDL写的一个小游戏

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Mon Jun 04 10:46:56 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off VGAps2 -c VGAps2
Info: Selected device EP1C6Q240C8 for design "VGAps2"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C12Q240C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 24
    Info: Pin ~ASDO~ is reserved at location 37
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk50m" to use Global clock in PIN 28
Info: Automatically promoted some destinations of signal "vgaCalc:u2|VgaInterface:u1|clk" to use Global clock
    Info: Destination "vgaCalc:u2|VgaInterface:u1|clk" may be non-global or may not use global clock
    Info: Destination "Readkey:u1|clk_6m" may be non-global or may not use global clock
    Info: Destination "Readkey:u1|counter[1]" may be non-global or may not use global clock
Info: Automatically promoted signal "Readkey:u1|ps_clk" to use Global clock
Info: Automatically promoted some destinations of signal "Readkey:u1|tempenable" to use Global clock
    Info: Destination "vgaCalc:u2|Calc:u2|va[3]" may be non-global or may not use global clock
    Info: Destination "vgaCalc:u2|Calc:u2|vb[3]" may be non-global or may not use global clock
    Info: Destination "Readkey:u1|tempenable" may be non-global or may not use global clock
    Info: Destination "vgaCalc:u2|Calc:u2|COMREG~147" may be non-global or may not use global clock
    Info: Destination "vgaCalc:u2|Calc:u2|COMREG~148" may be non-global or may not use global clock
    Info: Destination "vgaCalc:u2|Calc:u2|COMREG~149" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "Readkey:u1|clk_6m" to use Global clock
    Info: Destination "Readkey:u1|clk_6m" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "reset" to use Global clock
    Info: Destination "vgaCalc:u2|Calc:u2|va[0]~274" may be non-global or may not use global clock
    Info: Destination "vgaCalc:u2|Calc:u2|vb[0]~336" may be non-global or may not use global clock
    Info: Destination "vgaCalc:u2|Calc:u2|opout[0]~178" may be non-global or may not use global clock
    Info: Destination "vgaCalc:u2|Calc:u2|op~309" may be non-global or may not use global clock
Info: Pin "reset" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 5.295 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y10; Fanout = 5; REG Node = 'calcdata[2]'
    Info: 2: + IC(2.164 ns) + CELL(0.292 ns) = 2.456 ns; Loc. = LAB_X28_Y13; Fanout = 15; COMB Node = 'vgaCalc:u2|Calc:u2|COMREG~148'
    Info: 3: + IC(0.539 ns) + CELL(0.114 ns) = 3.109 ns; Loc. = LAB_X28_Y13; Fanout = 1; COMB Node = 'vgaCalc:u2|Calc:u2|opout[0]~177'
    Info: 4: + IC(0.211 ns) + CELL(0.442 ns) = 3.762 ns; Loc. = LAB_X28_Y13; Fanout = 2; COMB Node = 'vgaCalc:u2|Calc:u2|opout[0]~178'
    Info: 5: + IC(0.666 ns) + CELL(0.867 ns) = 5.295 ns; Loc. = LAB_X27_Y13; Fanout = 1; REG Node = 'vgaCalc:u2|Calc:u2|opout[0]'
    Info: Total cell delay = 1.715 ns ( 32.39 % )
    Info: Total interconnect delay = 3.580 ns ( 67.61 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 3%
    Info: The peak interconnect region extends from location X12_Y11 to location X23_Y21
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: Following 8 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin temp[0] has VCC driving its datain port
    Info: Pin temp[1] has VCC driving its datain port
    Info: Pin temp[2] has VCC driving its datain port
    Info: Pin temp[3] has VCC driving its datain port
    Info: Pin temp[4] has VCC driving its datain port
    Info: Pin temp[5] has VCC driving its datain port
    Info: Pin temp[6] has VCC driving its datain port
    Info: Pin temp[7] has VCC driving its datain port
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 177 megabytes of memory during processing
    Info: Processing ended: Mon Jun 04 10:47:05 2007
    Info: Elapsed time: 00:00:09