vgaps2.hif

用VHDL写的一个小游戏

Version 6.1 Build 201 11/27/2006 SJ Full Version
35
1935
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
vgaCalc
# storage
db|VGAps2.(2).cnf
db|VGAps2.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
vgaCalc.vhd
1920af636b96188670a567f5d9a676ff
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(datain1)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
vgaCalc:u2
}
# end
# entity
VgaInterface
# storage
db|VGAps2.(3).cnf
db|VGAps2.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
Vgainterface.vhd
624a44ef2cd29a51075207267b83488
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(pid_vga_data)
23 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
vgaCalc:u2|VgaInterface:u1
}
# end
# entity
rom1
# storage
db|VGAps2.(4).cnf
db|VGAps2.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rom1.vhd
cb72b7c4c528edf82dad6c937ee49f59
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
15 downto 0
PARAMETER_STRING
USR
 constraint(q)
0 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
vgaCalc:u2|VgaInterface:u1|rom1:u1
}
# end
# entity
altsyncram
# storage
db|VGAps2.(5).cnf
db|VGAps2.(5).cnf
# case_insensitive
# source_file
..|..|..|..|..|altera|61|quartus|libraries|megafunctions|altsyncram.tdf
82b9e86c1df4d3a925c3859b8da0bf
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
1
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
16
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
65536
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
picture.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_3b31
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a15
-1
3
address_a14
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
..|..|..|..|..|altera|61|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|..|..|altera|61|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|..|..|altera|61|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|..|..|altera|61|quartus|libraries|megafunctions|aglobal61.inc
b513fb574ceb8f5886cd4ba429e82ec
..|..|..|..|..|altera|61|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|..|..|altera|61|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|..|..|altera|61|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|..|..|altera|61|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
..|..|..|..|..|altera|61|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_3b31
# storage
db|VGAps2.(6).cnf
db|VGAps2.(6).cnf
# case_insensitive
# source_file
db|altsyncram_3b31.tdf
cc7dc6b9919ca5714c9b3d832e919d8
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a15
-1
3
address_a14
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3