vgaps2.tan.qmsg

用VHDL写的一个小游戏

{ "Info" "ITDB_TSU_RESULT" "vgaCalc:u2\|Calc:u2\|opout\[0\] reset clk50m 8.371 ns register " "Info: tsu for register \"vgaCalc:u2\|Calc:u2\|opout\[0\]\" (data pin = \"reset\", clock pin = \"clk50m\") is 8.371 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.296 ns + Longest pin register " "Info: + Longest pin to register delay is 11.296 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns reset 1 PIN PIN_233 51 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_233; Fanout = 51; PIN Node = 'reset'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "VGAps2.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/VGAps2.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.630 ns) + CELL(0.590 ns) 9.695 ns vgaCalc:u2\|Calc:u2\|opout\[0\]~178 2 COMB LC_X28_Y13_N4 2 " "Info: 2: + IC(7.630 ns) + CELL(0.590 ns) = 9.695 ns; Loc. = LC_X28_Y13_N4; Fanout = 2; COMB Node = 'vgaCalc:u2\|Calc:u2\|opout\[0\]~178'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.220 ns" { reset vgaCalc:u2|Calc:u2|opout[0]~178 } "NODE_NAME" } } { "Calc.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Calc.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.734 ns) + CELL(0.867 ns) 11.296 ns vgaCalc:u2\|Calc:u2\|opout\[0\] 3 REG LC_X27_Y13_N6 1 " "Info: 3: + IC(0.734 ns) + CELL(0.867 ns) = 11.296 ns; Loc. = LC_X27_Y13_N6; Fanout = 1; REG Node = 'vgaCalc:u2\|Calc:u2\|opout\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.601 ns" { vgaCalc:u2|Calc:u2|opout[0]~178 vgaCalc:u2|Calc:u2|opout[0] } "NODE_NAME" } } { "Calc.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Calc.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.932 ns ( 25.96 % ) " "Info: Total cell delay = 2.932 ns ( 25.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.364 ns ( 74.04 % ) " "Info: Total interconnect delay = 8.364 ns ( 74.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "11.296 ns" { reset vgaCalc:u2|Calc:u2|opout[0]~178 vgaCalc:u2|Calc:u2|opout[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "11.296 ns" { reset reset~out0 vgaCalc:u2|Calc:u2|opout[0]~178 vgaCalc:u2|Calc:u2|opout[0] } { 0.000ns 0.000ns 7.630ns 0.734ns } { 0.000ns 1.475ns 0.590ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "Calc.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Calc.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50m destination 2.962 ns - Shortest register " "Info: - Shortest clock path from clock \"clk50m\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk50m 1 CLK PIN_28 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 19; CLK Node = 'clk50m'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk50m } "NODE_NAME" } } { "VGAps2.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/VGAps2.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns vgaCalc:u2\|Calc:u2\|opout\[0\] 2 REG LC_X27_Y13_N6 1 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X27_Y13_N6; Fanout = 1; REG Node = 'vgaCalc:u2\|Calc:u2\|opout\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clk50m vgaCalc:u2|Calc:u2|opout[0] } "NODE_NAME" } } { "Calc.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Calc.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk50m vgaCalc:u2|Calc:u2|opout[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk50m clk50m~out0 vgaCalc:u2|Calc:u2|opout[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "11.296 ns" { reset vgaCalc:u2|Calc:u2|opout[0]~178 vgaCalc:u2|Calc:u2|opout[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "11.296 ns" { reset reset~out0 vgaCalc:u2|Calc:u2|opout[0]~178 vgaCalc:u2|Calc:u2|opout[0] } { 0.000ns 0.000ns 7.630ns 0.734ns } { 0.000ns 1.475ns 0.590ns 0.867ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk50m vgaCalc:u2|Calc:u2|opout[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk50m clk50m~out0 vgaCalc:u2|Calc:u2|opout[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk50m vga_r vgaCalc:u2\|VgaInterface:u1\|pod_vga_b 13.043 ns register " "Info: tco from clock \"clk50m\" to destination pin \"vga_r\" through register \"vgaCalc:u2\|VgaInterface:u1\|pod_vga_b\" is 13.043 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50m source 7.408 ns + Longest register " "Info: + Longest clock path from clock \"clk50m\" to source register is 7.408 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk50m 1 CLK PIN_28 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 19; CLK Node = 'clk50m'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk50m } "NODE_NAME" } } { "VGAps2.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/VGAps2.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns vgaCalc:u2\|VgaInterface:u1\|clk 2 REG LC_X8_Y10_N2 118 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N2; Fanout = 118; REG Node = 'vgaCalc:u2\|VgaInterface:u1\|clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk50m vgaCalc:u2|VgaInterface:u1|clk } "NODE_NAME" } } { "Vgainterface.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Vgainterface.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 7.408 ns vgaCalc:u2\|VgaInterface:u1\|pod_vga_b 3 REG LC_X20_Y16_N2 3 " "Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 7.408 ns; Loc. = LC_X20_Y16_N2; Fanout = 3; REG Node = 'vgaCalc:u2\|VgaInterface:u1\|pod_vga_b'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.259 ns" { vgaCalc:u2|VgaInterface:u1|clk vgaCalc:u2|VgaInterface:u1|pod_vga_b } "NODE_NAME" } } { "Vgainterface.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Vgainterface.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.05 % ) " "Info: Total cell delay = 3.115 ns ( 42.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.293 ns ( 57.95 % ) " "Info: Total interconnect delay = 4.293 ns ( 57.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { clk50m vgaCalc:u2|VgaInterface:u1|clk vgaCalc:u2|VgaInterface:u1|pod_vga_b } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { clk50m clk50m~out0 vgaCalc:u2|VgaInterface:u1|clk vgaCalc:u2|VgaInterface:u1|pod_vga_b } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Vgainterface.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Vgainterface.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.411 ns + Longest register pin " "Info: + Longest register to pin delay is 5.411 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vgaCalc:u2\|VgaInterface:u1\|pod_vga_b 1 REG LC_X20_Y16_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y16_N2; Fanout = 3; REG Node = 'vgaCalc:u2\|VgaInterface:u1\|pod_vga_b'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { vgaCalc:u2|VgaInterface:u1|pod_vga_b } "NODE_NAME" } } { "Vgainterface.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Vgainterface.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.303 ns) + CELL(2.108 ns) 5.411 ns vga_r 2 PIN PIN_226 0 " "Info: 2: + IC(3.303 ns) + CELL(2.108 ns) = 5.411 ns; Loc. = PIN_226; Fanout = 0; PIN Node = 'vga_r'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.411 ns" { vgaCalc:u2|VgaInterface:u1|pod_vga_b vga_r } "NODE_NAME" } } { "VGAps2.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/VGAps2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 38.96 % ) " "Info: Total cell delay = 2.108 ns ( 38.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.303 ns ( 61.04 % ) " "Info: Total interconnect delay = 3.303 ns ( 61.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.411 ns" { vgaCalc:u2|VgaInterface:u1|pod_vga_b vga_r } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.411 ns" { vgaCalc:u2|VgaInterface:u1|pod_vga_b vga_r } { 0.000ns 3.303ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { clk50m vgaCalc:u2|VgaInterface:u1|clk vgaCalc:u2|VgaInterface:u1|pod_vga_b } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { clk50m clk50m~out0 vgaCalc:u2|VgaInterface:u1|clk vgaCalc:u2|VgaInterface:u1|pod_vga_b } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.411 ns" { vgaCalc:u2|VgaInterface:u1|pod_vga_b vga_r } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.411 ns" { vgaCalc:u2|VgaInterface:u1|pod_vga_b vga_r } { 0.000ns 3.303ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "Readkey:u1\|ps_data kbdata clk50m 0.781 ns register " "Info: th for register \"Readkey:u1\|ps_data\" (data pin = \"kbdata\", clock pin = \"clk50m\") is 0.781 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50m destination 7.816 ns + Longest register " "Info: + Longest clock path from clock \"clk50m\" to destination register is 7.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk50m 1 CLK PIN_28 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 19; CLK Node = 'clk50m'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk50m } "NODE_NAME" } } { "VGAps2.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/VGAps2.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns Readkey:u1\|clk_6m 2 REG LC_X24_Y10_N2 3 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X24_Y10_N2; Fanout = 3; REG Node = 'Readkey:u1\|clk_6m'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.697 ns" { clk50m Readkey:u1|clk_6m } "NODE_NAME" } } { "Readkey.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Readkey.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.939 ns) + CELL(0.711 ns) 7.816 ns Readkey:u1\|ps_data 3 REG LC_X15_Y16_N2 8 " "Info: 3: + IC(3.939 ns) + CELL(0.711 ns) = 7.816 ns; Loc. = LC_X15_Y16_N2; Fanout = 8; REG Node = 'Readkey:u1\|ps_data'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.650 ns" { Readkey:u1|clk_6m Readkey:u1|ps_data } "NODE_NAME" } } { "Readkey.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Readkey.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.85 % ) " "Info: Total cell delay = 3.115 ns ( 39.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.701 ns ( 60.15 % ) " "Info: Total interconnect delay = 4.701 ns ( 60.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.816 ns" { clk50m Readkey:u1|clk_6m Readkey:u1|ps_data } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.816 ns" { clk50m clk50m~out0 Readkey:u1|clk_6m Readkey:u1|ps_data } { 0.000ns 0.000ns 0.762ns 3.939ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "Readkey.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Readkey.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.050 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.050 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns kbdata 1 PIN PIN_215 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_215; Fanout = 1; PIN Node = 'kbdata'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { kbdata } "NODE_NAME" } } { "VGAps2.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/VGAps2.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.460 ns) + CELL(0.115 ns) 7.050 ns Readkey:u1\|ps_data 2 REG LC_X15_Y16_N2 8 " "Info: 2: + IC(5.460 ns) + CELL(0.115 ns) = 7.050 ns; Loc. = LC_X15_Y16_N2; Fanout = 8; REG Node = 'Readkey:u1\|ps_data'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.575 ns" { kbdata Readkey:u1|ps_data } "NODE_NAME" } } { "Readkey.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Readkey.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns ( 22.55 % ) " "Info: Total cell delay = 1.590 ns ( 22.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.460 ns ( 77.45 % ) " "Info: Total interconnect delay = 5.460 ns ( 77.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.050 ns" { kbdata Readkey:u1|ps_data } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.050 ns" { kbdata kbdata~out0 Readkey:u1|ps_data } { 0.000ns 0.000ns 5.460ns } { 0.000ns 1.475ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.816 ns" { clk50m Readkey:u1|clk_6m Readkey:u1|ps_data } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.816 ns" { clk50m clk50m~out0 Readkey:u1|clk_6m Readkey:u1|ps_data } { 0.000ns 0.000ns 0.762ns 3.939ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.050 ns" { kbdata Readkey:u1|ps_data } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.050 ns" { kbdata kbdata~out0 Readkey:u1|ps_data } { 0.000ns 0.000ns 5.460ns } { 0.000ns 1.475ns 0.115ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "105 " "Info: Allocated 105 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 04 10:47:20 2007 " "Info: Processing ended: Mon Jun 04 10:47:20 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}