vgaps2.tan.qmsg

用VHDL写的一个小游戏

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Readkey:u1\|clk_6m " "Info: Detected ripple clock \"Readkey:u1\|clk_6m\" as buffer" {  } { { "Readkey.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Readkey.vhd" 26 -1 0 } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "Readkey:u1\|clk_6m" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "Readkey:u1\|ps_clk " "Info: Detected ripple clock \"Readkey:u1\|ps_clk\" as buffer" {  } { { "Readkey.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Readkey.vhd" 25 -1 0 } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "Readkey:u1\|ps_clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "Readkey:u1\|tempenable " "Info: Detected ripple clock \"Readkey:u1\|tempenable\" as buffer" {  } { { "Readkey.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Readkey.vhd" 57 -1 0 } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "Readkey:u1\|tempenable" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "vgaCalc:u2\|VgaInterface:u1\|clk " "Info: Detected ripple clock \"vgaCalc:u2\|VgaInterface:u1\|clk\" as buffer" {  } { { "Vgainterface.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Vgainterface.vhd" 35 -1 0 } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "vgaCalc:u2\|VgaInterface:u1\|clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk50m register Readkey:u1\|tempenable register vgaCalc:u2\|Calc:u2\|va\[0\] 36.06 MHz 27.734 ns Internal " "Info: Clock \"clk50m\" has Internal fmax of 36.06 MHz between source register \"Readkey:u1\|tempenable\" and destination register \"vgaCalc:u2\|Calc:u2\|va\[0\]\" (period= 27.734 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.305 ns + Longest register register " "Info: + Longest register to register delay is 4.305 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Readkey:u1\|tempenable 1 REG LC_X27_Y12_N2 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y12_N2; Fanout = 12; REG Node = 'Readkey:u1\|tempenable'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { Readkey:u1|tempenable } "NODE_NAME" } } { "Readkey.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Readkey.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.335 ns) + CELL(0.292 ns) 1.627 ns vgaCalc:u2\|Calc:u2\|COMREG~148 2 COMB LC_X28_Y13_N2 15 " "Info: 2: + IC(1.335 ns) + CELL(0.292 ns) = 1.627 ns; Loc. = LC_X28_Y13_N2; Fanout = 15; COMB Node = 'vgaCalc:u2\|Calc:u2\|COMREG~148'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.627 ns" { Readkey:u1|tempenable vgaCalc:u2|Calc:u2|COMREG~148 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.240 ns) + CELL(0.114 ns) 2.981 ns vgaCalc:u2\|Calc:u2\|va\[0\]~274 3 COMB LC_X26_Y13_N6 4 " "Info: 3: + IC(1.240 ns) + CELL(0.114 ns) = 2.981 ns; Loc. = LC_X26_Y13_N6; Fanout = 4; COMB Node = 'vgaCalc:u2\|Calc:u2\|va\[0\]~274'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.354 ns" { vgaCalc:u2|Calc:u2|COMREG~148 vgaCalc:u2|Calc:u2|va[0]~274 } "NODE_NAME" } } { "Calc.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Calc.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.457 ns) + CELL(0.867 ns) 4.305 ns vgaCalc:u2\|Calc:u2\|va\[0\] 4 REG LC_X26_Y13_N4 8 " "Info: 4: + IC(0.457 ns) + CELL(0.867 ns) = 4.305 ns; Loc. = LC_X26_Y13_N4; Fanout = 8; REG Node = 'vgaCalc:u2\|Calc:u2\|va\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.324 ns" { vgaCalc:u2|Calc:u2|va[0]~274 vgaCalc:u2|Calc:u2|va[0] } "NODE_NAME" } } { "Calc.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Calc.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.273 ns ( 29.57 % ) " "Info: Total cell delay = 1.273 ns ( 29.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.032 ns ( 70.43 % ) " "Info: Total interconnect delay = 3.032 ns ( 70.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.305 ns" { Readkey:u1|tempenable vgaCalc:u2|Calc:u2|COMREG~148 vgaCalc:u2|Calc:u2|va[0]~274 vgaCalc:u2|Calc:u2|va[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.305 ns" { Readkey:u1|tempenable vgaCalc:u2|Calc:u2|COMREG~148 vgaCalc:u2|Calc:u2|va[0]~274 vgaCalc:u2|Calc:u2|va[0] } { 0.000ns 1.335ns 1.240ns 0.457ns } { 0.000ns 0.292ns 0.114ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-9.301 ns - Smallest " "Info: - Smallest clock skew is -9.301 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50m destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"clk50m\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk50m 1 CLK PIN_28 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 19; CLK Node = 'clk50m'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk50m } "NODE_NAME" } } { "VGAps2.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/VGAps2.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns vgaCalc:u2\|Calc:u2\|va\[0\] 2 REG LC_X26_Y13_N4 8 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X26_Y13_N4; Fanout = 8; REG Node = 'vgaCalc:u2\|Calc:u2\|va\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clk50m vgaCalc:u2|Calc:u2|va[0] } "NODE_NAME" } } { "Calc.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Calc.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk50m vgaCalc:u2|Calc:u2|va[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk50m clk50m~out0 vgaCalc:u2|Calc:u2|va[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50m source 12.263 ns - Longest register " "Info: - Longest clock path from clock \"clk50m\" to source register is 12.263 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk50m 1 CLK PIN_28 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 19; CLK Node = 'clk50m'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk50m } "NODE_NAME" } } { "VGAps2.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/VGAps2.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns Readkey:u1\|clk_6m 2 REG LC_X24_Y10_N2 3 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X24_Y10_N2; Fanout = 3; REG Node = 'Readkey:u1\|clk_6m'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.697 ns" { clk50m Readkey:u1|clk_6m } "NODE_NAME" } } { "Readkey.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Readkey.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.927 ns) + CELL(0.935 ns) 8.028 ns Readkey:u1\|ps_clk 3 REG LC_X27_Y10_N4 13 " "Info: 3: + IC(3.927 ns) + CELL(0.935 ns) = 8.028 ns; Loc. = LC_X27_Y10_N4; Fanout = 13; REG Node = 'Readkey:u1\|ps_clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.862 ns" { Readkey:u1|clk_6m Readkey:u1|ps_clk } "NODE_NAME" } } { "Readkey.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Readkey.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.524 ns) + CELL(0.711 ns) 12.263 ns Readkey:u1\|tempenable 4 REG LC_X27_Y12_N2 12 " "Info: 4: + IC(3.524 ns) + CELL(0.711 ns) = 12.263 ns; Loc. = LC_X27_Y12_N2; Fanout = 12; REG Node = 'Readkey:u1\|tempenable'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.235 ns" { Readkey:u1|ps_clk Readkey:u1|tempenable } "NODE_NAME" } } { "Readkey.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Readkey.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 33.03 % ) " "Info: Total cell delay = 4.050 ns ( 33.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.213 ns ( 66.97 % ) " "Info: Total interconnect delay = 8.213 ns ( 66.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "12.263 ns" { clk50m Readkey:u1|clk_6m Readkey:u1|ps_clk Readkey:u1|tempenable } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "12.263 ns" { clk50m clk50m~out0 Readkey:u1|clk_6m Readkey:u1|ps_clk Readkey:u1|tempenable } { 0.000ns 0.000ns 0.762ns 3.927ns 3.524ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk50m vgaCalc:u2|Calc:u2|va[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk50m clk50m~out0 vgaCalc:u2|Calc:u2|va[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "12.263 ns" { clk50m Readkey:u1|clk_6m Readkey:u1|ps_clk Readkey:u1|tempenable } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "12.263 ns" { clk50m clk50m~out0 Readkey:u1|clk_6m Readkey:u1|ps_clk Readkey:u1|tempenable } { 0.000ns 0.000ns 0.762ns 3.927ns 3.524ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Readkey.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Readkey.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "Calc.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Calc.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "Readkey.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Readkey.vhd" 57 -1 0 } } { "Calc.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Calc.vhd" 33 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.305 ns" { Readkey:u1|tempenable vgaCalc:u2|Calc:u2|COMREG~148 vgaCalc:u2|Calc:u2|va[0]~274 vgaCalc:u2|Calc:u2|va[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.305 ns" { Readkey:u1|tempenable vgaCalc:u2|Calc:u2|COMREG~148 vgaCalc:u2|Calc:u2|va[0]~274 vgaCalc:u2|Calc:u2|va[0] } { 0.000ns 1.335ns 1.240ns 0.457ns } { 0.000ns 0.292ns 0.114ns 0.867ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk50m vgaCalc:u2|Calc:u2|va[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk50m clk50m~out0 vgaCalc:u2|Calc:u2|va[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "12.263 ns" { clk50m Readkey:u1|clk_6m Readkey:u1|ps_clk Readkey:u1|tempenable } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "12.263 ns" { clk50m clk50m~out0 Readkey:u1|clk_6m Readkey:u1|ps_clk Readkey:u1|tempenable } { 0.000ns 0.000ns 0.762ns 3.927ns 3.524ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk50m 122 " "Warning: Circuit may not operate. Detected 122 non-operational path(s) clocked by clock \"clk50m\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "vgaCalc:u2\|Calc:u2\|STX.st3 vgaCalc:u2\|VgaInterface:u1\|vga_data\[12\] clk50m 3.187 ns " "Info: Found hold time violation between source  pin or register \"vgaCalc:u2\|Calc:u2\|STX.st3\" and destination pin or register \"vgaCalc:u2\|VgaInterface:u1\|vga_data\[12\]\" for clock \"clk50m\" (Hold time is 3.187 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.446 ns + Largest " "Info: + Largest clock skew is 4.446 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50m destination 7.408 ns + Longest register " "Info: + Longest clock path from clock \"clk50m\" to destination register is 7.408 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk50m 1 CLK PIN_28 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 19; CLK Node = 'clk50m'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk50m } "NODE_NAME" } } { "VGAps2.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/VGAps2.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns vgaCalc:u2\|VgaInterface:u1\|clk 2 REG LC_X8_Y10_N2 118 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N2; Fanout = 118; REG Node = 'vgaCalc:u2\|VgaInterface:u1\|clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk50m vgaCalc:u2|VgaInterface:u1|clk } "NODE_NAME" } } { "Vgainterface.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Vgainterface.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 7.408 ns vgaCalc:u2\|VgaInterface:u1\|vga_data\[12\] 3 REG LC_X25_Y13_N7 1 " "Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 7.408 ns; Loc. = LC_X25_Y13_N7; Fanout = 1; REG Node = 'vgaCalc:u2\|VgaInterface:u1\|vga_data\[12\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.259 ns" { vgaCalc:u2|VgaInterface:u1|clk vgaCalc:u2|VgaInterface:u1|vga_data[12] } "NODE_NAME" } } { "Vgainterface.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Vgainterface.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.05 % ) " "Info: Total cell delay = 3.115 ns ( 42.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.293 ns ( 57.95 % ) " "Info: Total interconnect delay = 4.293 ns ( 57.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { clk50m vgaCalc:u2|VgaInterface:u1|clk vgaCalc:u2|VgaInterface:u1|vga_data[12] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { clk50m clk50m~out0 vgaCalc:u2|VgaInterface:u1|clk vgaCalc:u2|VgaInterface:u1|vga_data[12] } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50m source 2.962 ns - Shortest register " "Info: - Shortest clock path from clock \"clk50m\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk50m 1 CLK PIN_28 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 19; CLK Node = 'clk50m'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk50m } "NODE_NAME" } } { "VGAps2.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/VGAps2.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns vgaCalc:u2\|Calc:u2\|STX.st3 2 REG LC_X25_Y13_N9 7 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X25_Y13_N9; Fanout = 7; REG Node = 'vgaCalc:u2\|Calc:u2\|STX.st3'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clk50m vgaCalc:u2|Calc:u2|STX.st3 } "NODE_NAME" } } { "Calc.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Calc.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk50m vgaCalc:u2|Calc:u2|STX.st3 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk50m clk50m~out0 vgaCalc:u2|Calc:u2|STX.st3 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { clk50m vgaCalc:u2|VgaInterface:u1|clk vgaCalc:u2|VgaInterface:u1|vga_data[12] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { clk50m clk50m~out0 vgaCalc:u2|VgaInterface:u1|clk vgaCalc:u2|VgaInterface:u1|vga_data[12] } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk50m vgaCalc:u2|Calc:u2|STX.st3 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk50m clk50m~out0 vgaCalc:u2|Calc:u2|STX.st3 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "Calc.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Calc.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.050 ns - Shortest register register " "Info: - Shortest register to register delay is 1.050 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vgaCalc:u2\|Calc:u2\|STX.st3 1 REG LC_X25_Y13_N9 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y13_N9; Fanout = 7; REG Node = 'vgaCalc:u2\|Calc:u2\|STX.st3'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { vgaCalc:u2|Calc:u2|STX.st3 } "NODE_NAME" } } { "Calc.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Calc.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.572 ns) + CELL(0.478 ns) 1.050 ns vgaCalc:u2\|VgaInterface:u1\|vga_data\[12\] 2 REG LC_X25_Y13_N7 1 " "Info: 2: + IC(0.572 ns) + CELL(0.478 ns) = 1.050 ns; Loc. = LC_X25_Y13_N7; Fanout = 1; REG Node = 'vgaCalc:u2\|VgaInterface:u1\|vga_data\[12\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.050 ns" { vgaCalc:u2|Calc:u2|STX.st3 vgaCalc:u2|VgaInterface:u1|vga_data[12] } "NODE_NAME" } } { "Vgainterface.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Vgainterface.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns ( 45.52 % ) " "Info: Total cell delay = 0.478 ns ( 45.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.572 ns ( 54.48 % ) " "Info: Total interconnect delay = 0.572 ns ( 54.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.050 ns" { vgaCalc:u2|Calc:u2|STX.st3 vgaCalc:u2|VgaInterface:u1|vga_data[12] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "1.050 ns" { vgaCalc:u2|Calc:u2|STX.st3 vgaCalc:u2|VgaInterface:u1|vga_data[12] } { 0.000ns 0.572ns } { 0.000ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "Vgainterface.vhd" "" { Text "C:/Documents and Settings/new/桌面/VGAps2final/VGAps2final/Vgainterface.vhd" 69 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { clk50m vgaCalc:u2|VgaInterface:u1|clk vgaCalc:u2|VgaInterface:u1|vga_data[12] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { clk50m clk50m~out0 vgaCalc:u2|VgaInterface:u1|clk vgaCalc:u2|VgaInterface:u1|vga_data[12] } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk50m vgaCalc:u2|Calc:u2|STX.st3 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk50m clk50m~out0 vgaCalc:u2|Calc:u2|STX.st3 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.050 ns" { vgaCalc:u2|Calc:u2|STX.st3 vgaCalc:u2|VgaInterface:u1|vga_data[12] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "1.050 ns" { vgaCalc:u2|Calc:u2|STX.st3 vgaCalc:u2|VgaInterface:u1|vga_data[12] } { 0.000ns 0.572ns } { 0.000ns 0.478ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}