mux_gcb.tdf

用VHDL写的一个小游戏

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_SIZE=16 LPM_WIDTH=1 LPM_WIDTHS=4 data result sel
--VERSION_BEGIN 6.1 cbx_lpm_mux 2006:04:25:15:10:08:SJ cbx_mgl 2006:10:27:16:08:48:SJ  VERSION_END


--  Copyright (C) 1991-2006 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 10 
SUBDESIGN mux_gcb
( 
	data[15..0]	:	input;
	result[0..0]	:	output;
	sel[3..0]	:	input;
) 
VARIABLE 
	result_node[0..0]	: WIRE;
	sel_ffs_wire[3..0]	: WIRE;
	sel_node[3..0]	: WIRE;
	w_data131w[3..0]	: WIRE;
	w_data132w[3..0]	: WIRE;
	w_data133w[3..0]	: WIRE;
	w_data134w[3..0]	: WIRE;
	w_data76w[15..0]	: WIRE;
	w_result127w	: WIRE;
	w_result128w	: WIRE;
	w_result129w	: WIRE;
	w_result130w	: WIRE;
	w_result141w	: WIRE;
	w_result162w	: WIRE;
	w_result179w	: WIRE;
	w_result196w	: WIRE;
	w_result212w	: WIRE;
	w_sel135w[1..0]	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( (((w_result128w & sel_node[2..2]) & (! w_result212w)) # (w_result212w & (w_result130w # (! sel_node[2..2])))));
	sel_ffs_wire[] = ( sel[3..0]);
	sel_node[] = ( sel_ffs_wire[3..2], sel[1..0]);
	w_data131w[3..0] = w_data76w[3..0];
	w_data132w[3..0] = w_data76w[7..4];
	w_data133w[3..0] = w_data76w[11..8];
	w_data134w[3..0] = w_data76w[15..12];
	w_data76w[] = ( data[15..0]);
	w_result127w = (((w_data131w[1..1] & w_sel135w[0..0]) & (! w_result141w)) # (w_result141w & (w_data131w[3..3] # (! w_sel135w[0..0]))));
	w_result128w = (((w_data132w[1..1] & w_sel135w[0..0]) & (! w_result162w)) # (w_result162w & (w_data132w[3..3] # (! w_sel135w[0..0]))));
	w_result129w = (((w_data133w[1..1] & w_sel135w[0..0]) & (! w_result179w)) # (w_result179w & (w_data133w[3..3] # (! w_sel135w[0..0]))));
	w_result130w = (((w_data134w[1..1] & w_sel135w[0..0]) & (! w_result196w)) # (w_result196w & (w_data134w[3..3] # (! w_sel135w[0..0]))));
	w_result141w = (((w_data131w[0..0] & (! w_sel135w[1..1])) & (! w_sel135w[0..0])) # (w_sel135w[1..1] & (w_sel135w[0..0] # w_data131w[2..2])));
	w_result162w = (((w_data132w[0..0] & (! w_sel135w[1..1])) & (! w_sel135w[0..0])) # (w_sel135w[1..1] & (w_sel135w[0..0] # w_data132w[2..2])));
	w_result179w = (((w_data133w[0..0] & (! w_sel135w[1..1])) & (! w_sel135w[0..0])) # (w_sel135w[1..1] & (w_sel135w[0..0] # w_data133w[2..2])));
	w_result196w = (((w_data134w[0..0] & (! w_sel135w[1..1])) & (! w_sel135w[0..0])) # (w_sel135w[1..1] & (w_sel135w[0..0] # w_data134w[2..2])));
	w_result212w = (((w_result127w & (! sel_node[3..3])) & (! sel_node[2..2])) # (sel_node[3..3] & (sel_node[2..2] # w_result129w)));
	w_sel135w[1..0] = sel_node[1..0];
END;
--VALID FILE