vgaps2.hier_info

用VHDL写的一个小游戏

|VGAps2
kbclk => Readkey:u1.clk
kbdata => Readkey:u1.ps2data
clk50m => vgaCalc:u2.clk1
clk50m => Readkey:u1.clk_50m
reset => vgaCalc:u2.reset1
vga_r <= vgaCalc:u2.out_vga_r
vga_g <= vgaCalc:u2.out_vga_g
vga_b <= vgaCalc:u2.out_vga_b
vga_hs <= vgaCalc:u2.out_vga_hs
vga_vs <= vgaCalc:u2.out_vga_vs
temp[0] <= <VCC>
temp[1] <= <VCC>
temp[2] <= <VCC>
temp[3] <= <VCC>
temp[4] <= <VCC>
temp[5] <= <VCC>
temp[6] <= <VCC>
temp[7] <= <VCC>


|VGAps2|Readkey:u1
clk => ps_clk.DATAIN
clk_50m => clk_6m.CLK
clk_50m => counter[0].CLK
clk_50m => counter[1].CLK
ps2data => ps_data.DATAIN
feedback <= tempenable.DB_MAX_OUTPUT_PORT_TYPE
key[0] <= tempcode[0].DB_MAX_OUTPUT_PORT_TYPE
key[1] <= tempcode[1].DB_MAX_OUTPUT_PORT_TYPE
key[2] <= tempcode[2].DB_MAX_OUTPUT_PORT_TYPE
key[3] <= tempcode[3].DB_MAX_OUTPUT_PORT_TYPE
key[4] <= tempcode[4].DB_MAX_OUTPUT_PORT_TYPE
key[5] <= tempcode[5].DB_MAX_OUTPUT_PORT_TYPE
key[6] <= tempcode[6].DB_MAX_OUTPUT_PORT_TYPE
key[7] <= tempcode[7].DB_MAX_OUTPUT_PORT_TYPE


|VGAps2|vgaCalc:u2
clk1 => Calc:u2.clk
clk1 => VgaInterface:u1.clk_0
enable1 => Calc:u2.enable
reset1 => Calc:u2.reset
reset1 => VgaInterface:u1.reset
datain1[0] => Calc:u2.datain[0]
datain1[1] => Calc:u2.datain[1]
datain1[2] => Calc:u2.datain[2]
datain1[3] => Calc:u2.datain[3]
out_vga_r <= VgaInterface:u1.pod_vga_r
out_vga_g <= VgaInterface:u1.pod_vga_g
out_vga_b <= VgaInterface:u1.pod_vga_b
out_vga_hs <= VgaInterface:u1.poc_vga_hs
out_vga_vs <= VgaInterface:u1.poc_vga_vs


|VGAps2|vgaCalc:u2|VgaInterface:u1
reset => poc_vga_vs~reg0.ACLR
reset => poc_vga_hs~reg0.ACLR
reset => pod_vga_b~reg0.ACLR
reset => pod_vga_g~reg0.ACLR
reset => pod_vga_r~reg0.ACLR
reset => vs_p.PRESET
reset => hs_p.PRESET
reset => vector_y[0].ACLR
reset => vector_y[1].ACLR
reset => vector_y[2].ACLR
reset => vector_y[3].ACLR
reset => vector_y[4].ACLR
reset => vector_y[5].ACLR
reset => vector_y[6].ACLR
reset => vector_y[7].ACLR
reset => vector_y[8].ACLR
reset => vector_x[0].ACLR
reset => vector_x[1].ACLR
reset => vector_x[2].ACLR
reset => vector_x[3].ACLR
reset => vector_x[4].ACLR
reset => vector_x[5].ACLR
reset => vector_x[6].ACLR
reset => vector_x[7].ACLR
reset => vector_x[8].ACLR
reset => vector_x[9].ACLR
reset => vga_data[0].ACLR
reset => vga_data[1].ACLR
reset => vga_data[2].ACLR
reset => vga_data[3].ACLR
reset => vga_data[4].ACLR
reset => vga_data[5].ACLR
reset => vga_data[6].ACLR
reset => vga_data[7].ACLR
reset => vga_data[8].ACLR
reset => vga_data[9].ACLR
reset => vga_data[10].ACLR
reset => vga_data[11].ACLR
reset => vga_data[12].ACLR
reset => vga_data[13].ACLR
reset => vga_data[14].ACLR
reset => vga_data[15].ACLR
reset => vga_data[16].ACLR
reset => vga_data[17].ACLR
reset => vga_data[18].ACLR
reset => vga_data[19].ACLR
reset => vga_data[20].ACLR
reset => vga_data[21].ACLR
reset => vga_data[22].ACLR
reset => vga_data[23].ACLR
clk_0 => clk.CLK
pid_vga_data[0] => vga_data[0].DATAIN
pid_vga_data[1] => vga_data[1].DATAIN
pid_vga_data[2] => vga_data[2].DATAIN
pid_vga_data[3] => vga_data[3].DATAIN
pid_vga_data[4] => vga_data[4].DATAIN
pid_vga_data[5] => vga_data[5].DATAIN
pid_vga_data[6] => vga_data[6].DATAIN
pid_vga_data[7] => vga_data[7].DATAIN
pid_vga_data[8] => vga_data[8].DATAIN
pid_vga_data[9] => vga_data[9].DATAIN
pid_vga_data[10] => vga_data[10].DATAIN
pid_vga_data[11] => vga_data[11].DATAIN
pid_vga_data[12] => vga_data[12].DATAIN
pid_vga_data[13] => vga_data[13].DATAIN
pid_vga_data[14] => vga_data[14].DATAIN
pid_vga_data[15] => vga_data[15].DATAIN
pid_vga_data[16] => vga_data[16].DATAIN
pid_vga_data[17] => vga_data[17].DATAIN
pid_vga_data[18] => vga_data[18].DATAIN
pid_vga_data[19] => vga_data[19].DATAIN
pid_vga_data[20] => vga_data[20].DATAIN
pid_vga_data[21] => vga_data[21].DATAIN
pid_vga_data[22] => vga_data[22].DATAIN
pid_vga_data[23] => vga_data[23].DATAIN
pod_vga_r <= pod_vga_r~reg0.DB_MAX_OUTPUT_PORT_TYPE
pod_vga_g <= pod_vga_g~reg0.DB_MAX_OUTPUT_PORT_TYPE
pod_vga_b <= pod_vga_b~reg0.DB_MAX_OUTPUT_PORT_TYPE
poc_vga_hs <= poc_vga_hs~reg0.DB_MAX_OUTPUT_PORT_TYPE
poc_vga_vs <= poc_vga_vs~reg0.DB_MAX_OUTPUT_PORT_TYPE


|VGAps2|vgaCalc:u2|VgaInterface:u1|rom1:u1
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
address[10] => altsyncram:altsyncram_component.address_a[10]
address[11] => altsyncram:altsyncram_component.address_a[11]
address[12] => altsyncram:altsyncram_component.address_a[12]
address[13] => altsyncram:altsyncram_component.address_a[13]
address[14] => altsyncram:altsyncram_component.address_a[14]
address[15] => altsyncram:altsyncram_component.address_a[15]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]


|VGAps2|vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_3b31:auto_generated.address_a[0]
address_a[1] => altsyncram_3b31:auto_generated.address_a[1]
address_a[2] => altsyncram_3b31:auto_generated.address_a[2]
address_a[3] => altsyncram_3b31:auto_generated.address_a[3]
address_a[4] => altsyncram_3b31:auto_generated.address_a[4]
address_a[5] => altsyncram_3b31:auto_generated.address_a[5]
address_a[6] => altsyncram_3b31:auto_generated.address_a[6]
address_a[7] => altsyncram_3b31:auto_generated.address_a[7]
address_a[8] => altsyncram_3b31:auto_generated.address_a[8]
address_a[9] => altsyncram_3b31:auto_generated.address_a[9]
address_a[10] => altsyncram_3b31:auto_generated.address_a[10]
address_a[11] => altsyncram_3b31:auto_generated.address_a[11]
address_a[12] => altsyncram_3b31:auto_generated.address_a[12]
address_a[13] => altsyncram_3b31:auto_generated.address_a[13]
address_a[14] => altsyncram_3b31:auto_generated.address_a[14]
address_a[15] => altsyncram_3b31:auto_generated.address_a[15]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_3b31:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_3b31:auto_generated.q_a[0]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|VGAps2|vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_3b31:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[10] => ram_block1a12.PORTAADDR10
address_a[10] => ram_block1a13.PORTAADDR10
address_a[10] => ram_block1a14.PORTAADDR10
address_a[10] => ram_block1a15.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
address_a[11] => ram_block1a8.PORTAADDR11
address_a[11] => ram_block1a9.PORTAADDR11
address_a[11] => ram_block1a10.PORTAADDR11
address_a[11] => ram_block1a11.PORTAADDR11
address_a[11] => ram_block1a12.PORTAADDR11
address_a[11] => ram_block1a13.PORTAADDR11
address_a[11] => ram_block1a14.PORTAADDR11
address_a[11] => ram_block1a15.PORTAADDR11
address_a[12] => address_reg_a[0].DATAIN
address_a[13] => address_reg_a[1].DATAIN
address_a[14] => address_reg_a[2].DATAIN
address_a[15] => address_reg_a[3].DATAIN
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => address_reg_a[3].CLK
clock0 => address_reg_a[2].CLK
clock0 => address_reg_a[1].CLK
clock0 => address_reg_a[0].CLK
clock0 => out_address_reg_a[3].CLK
clock0 => out_address_reg_a[2].CLK
clock0 => out_address_reg_a[1].CLK
clock0 => out_address_reg_a[0].CLK
q_a[0] <= mux_gcb:mux2.result[0]


|VGAps2|vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_3b31:auto_generated|mux_gcb:mux2
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE


|VGAps2|vgaCalc:u2|Calc:u2
clk => vb[0].CLK
clk => vb[1].CLK
clk => vb[2].CLK
clk => vb[3].CLK
clk => opout[0].CLK
clk => opout[1].CLK
clk => opout[2].CLK
clk => opout[3].CLK
clk => op.CLK
clk => va[0].CLK
clk => va[1].CLK
clk => va[2].CLK
clk => va[3].CLK
clk => STX~27.IN1
enable => COMREG~3.IN0
enable => COMREG~4.IN0