vgaps2.vhd

用VHDL写的一个小游戏

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--实验题号   : Ex5-1
--项目名称   : 键盘输入的计算器
--文件名     : VGAps2.vhd
--作者       : 田甲
--班号.      : 计45 
--创建日期   : 2006-05-25
--目标芯片   : EP1C6Q240C8
--电路模式   : 模式5
--功能描述   : 本文件给出了键盘输入的计算器的结构描述
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity VGAps2 is
port(kbclk, kbdata, clk50m, reset: IN STD_LOGIC; 
  		vga_r            :         out STD_LOGIC;
  		vga_g            :         out STD_LOGIC;
  		vga_b            :         out STD_LOGIC;
  		vga_hs           :         out STD_LOGIC;
  		vga_vs           :         out STD_LOGIC;
         temp        :         out std_logic_vector(7 downto 0)
        );
end entity;

architecture Impl of VGAps2 is

signal fb, tempphase, data, shiftflag, relflag: std_logic := '0';
signal calcdata: std_logic_vector(3 downto 0);
signal tempdata : std_logic_vector(7 downto 0);


component Readkey is
port(clk, clk_50m, ps2data: IN STD_LOGIC; 
  		feedback             :         out STD_LOGIC;
  		key                  :         out STD_LOGIC_VECTOR(7 downto 0)
        );
end component;

component vgaCalc is
port(clk1 , enable1 , reset1: IN STD_LOGIC; 
		datain1: IN STD_LOGIC_VECTOR(3 downto 0); 
  		out_vga_r            :         out STD_LOGIC;
  		out_vga_g            :         out STD_LOGIC;
  		out_vga_b            :         out STD_LOGIC;
  		out_vga_hs           :         out STD_LOGIC;
  		out_vga_vs           :         out STD_LOGIC
        );
end component;

begin
u1:Readkey port map
(clk => kbclk, ps2data => kbdata, clk_50m => clk50m, 
	feedback => fb, key => tempdata);
u2:vgaCalc port map
(clk1 => clk50m, enable1 => fb, reset1 => reset, datain1 => calcdata, 
 out_vga_r => vga_r, out_vga_g => vga_g, out_vga_b => vga_b, 
 out_vga_hs => vga_hs, out_vga_vs => vga_vs);
--temp<=tempdata;
temp<="11111111";
process(fb)
begin
	if fb'event and fb = '1' then
		if tempdata="11110000" then
			relflag<='1';
		else
			if relflag='0' then
				if tempdata="01000101" or tempdata=x"70" then
					calcdata<="0000";
				elsif tempdata="00010110" or tempdata=x"69" then
					calcdata<="0001";
				elsif tempdata="00011110" or tempdata=x"72" then
					calcdata<="0010";
				elsif tempdata="00100110" or tempdata=x"7A" then
					calcdata<="0011";
				elsif tempdata="00100101" or tempdata=x"6B" then
					calcdata<="0100";
				elsif tempdata="00101110" or tempdata=x"73" then
					calcdata<="0101";
				elsif tempdata="00110110" or tempdata=x"74" then
					calcdata<="0110";
				elsif tempdata="00111101" or tempdata=x"6C" then
					calcdata<="0111";
				elsif tempdata="00111110" or tempdata=x"75" then
					calcdata<="1000";
				elsif tempdata="01000110" or tempdata=x"7D" then
					calcdata<="1001";
				elsif tempdata="01001110" or tempdata=x"7B" then
					calcdata<="1011"; -- '-'
				elsif tempdata=x"5A" then
					calcdata<="1101"; -- \n
				elsif tempdata=x"79" then
					calcdata<="1010"; -- '+'
				elsif tempdata="01010101" then
					if shiftflag='0' then
						calcdata<="1100"; -- '='
					else
						calcdata<="1010"; -- '+'
					end if;
				elsif tempdata="00101001" then -- space
					calcdata<="1101"; -- restart
				elsif tempdata="00010010" or tempdata="01011001" then -- shift down
					shiftflag<='1';
				end if;
			else
				relflag <= '0';
				if tempdata="00010010" or tempdata="01011001" then -- shift up
					shiftflag<='0';
				end if;
			end if;
		end if;
	end if;
end process;
end architecture Impl;