vgacalc.vhd

用VHDL写的一个小游戏

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--实验题号   : Ex5-1
--项目名称   : VGA接口的计算器
--文件名     : vgacalc.vhd
--作者       : 田甲
--班号.      : 计45 
--创建日期   : 2006-05-25
--目标芯片   : EP1C6Q240C8
--电路模式   : 模式5
--功能描述   : 本文件给出了VGA接口的计算器的结构描述
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library ieee;
use ieee.std_logic_1164.all;

entity vgaCalc is
port(clk1 , enable1 , reset1: IN STD_LOGIC; 
		datain1: IN STD_LOGIC_VECTOR(3 downto 0); 
  		out_vga_r            :         out STD_LOGIC;
  		out_vga_g            :         out STD_LOGIC;
  		out_vga_b            :         out STD_LOGIC;
  		out_vga_hs           :         out STD_LOGIC;
  		out_vga_vs           :         out STD_LOGIC
        );
end entity;

architecture Impl of vgaCalc is
component Calc IS
PORT ( clk , enable , reset: IN STD_LOGIC; 
		datain: IN STD_LOGIC_VECTOR(3 downto 0); 
         Q : OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END component;

component VgaInterface is
 port(
  reset                :         in  STD_LOGIC;
  clk_0                :         in  STD_LOGIC;
  ----  These are the Signals connect with CalControl
  pid_vga_data         :         in  STD_LOGIC_VECTOR(23 downto 0);
  ----  These are the VGA Control Signal
  pod_vga_r            :         out STD_LOGIC;
  pod_vga_g            :         out STD_LOGIC;
  pod_vga_b            :         out STD_LOGIC;
  poc_vga_hs           :         out STD_LOGIC;
  poc_vga_vs           :         out STD_LOGIC
);
end component;

signal tempQ1, tempQ2:std_logic_vector(23 downto 0);
begin
u1:VgaInterface port map
(reset => reset1, clk_0 => clk1, pid_vga_data => tempQ2, 
 pod_vga_r => out_vga_r, pod_vga_g => out_vga_g, pod_vga_b => out_vga_b, 
 poc_vga_hs => out_vga_hs, poc_vga_vs => out_vga_vs);

u2:Calc port map
(clk => clk1, enable => enable1, reset => reset1, datain => datain1, Q => tempQ1);
tempQ2(23 downto 8) <= tempQ1(23 downto 8);
tempQ2(3 downto 0) <= tempQ1(3 downto 0);
process(tempQ1)
begin
	if tempQ1(7 downto 4) = "1110" then
		tempQ2(7 downto 4) <= "1011";
	elsif tempQ1(7 downto 4) = "0000" then
		tempQ2(7 downto 4) <= "1111";
	else
		tempQ2(7 downto 4) <= tempQ1(7 downto 4);
	end if;
end process;
end architecture Impl;