vgaps2.fit.eqn

用VHDL写的一个小游戏

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--D1_pod_vga_r is vgaCalc:u2|VgaInterface:u1|pod_vga_r at LC_X14_Y13_N6
--operation mode is normal

D1_pod_vga_r_lut_out = D1_enable & D1_vga_r;
D1_pod_vga_r = DFFEAS(D1_pod_vga_r_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , , , , , );


--D1_poc_vga_hs is vgaCalc:u2|VgaInterface:u1|poc_vga_hs at LC_X10_Y13_N4
--operation mode is normal

D1_poc_vga_hs_lut_out = !D1_hs_p;
D1_poc_vga_hs = DFFEAS(D1_poc_vga_hs_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , , , , , );


--D1_poc_vga_vs is vgaCalc:u2|VgaInterface:u1|poc_vga_vs at LC_X14_Y13_N7
--operation mode is normal

D1_poc_vga_vs_lut_out = !D1_vs_p;
D1_poc_vga_vs = DFFEAS(D1_poc_vga_vs_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , , , , , );


--D1_vga_r is vgaCalc:u2|VgaInterface:u1|vga_r at LC_X14_Y13_N3
--operation mode is normal

D1_vga_r_lut_out = J1L2 & !D1_en;
D1_vga_r = DFFEAS(D1_vga_r_lut_out, GLOBAL(D1_clk), VCC, , , , , , );


--D1_enable is vgaCalc:u2|VgaInterface:u1|enable at LC_X14_Y13_N8
--operation mode is normal

D1_enable_lut_out = !D1L611 & (!D1_vector_x[7] & !D1_vector_x[8] # !D1_vector_x[9]);
D1_enable = DFFEAS(D1_enable_lut_out, GLOBAL(D1_clk), VCC, , , , , , );


--D1_clk is vgaCalc:u2|VgaInterface:u1|clk at LC_X8_Y10_N5
--operation mode is normal

D1_clk_lut_out = !D1_clk;
D1_clk = DFFEAS(D1_clk_lut_out, GLOBAL(clk50m), VCC, , , , , , );


--D1_hs_p is vgaCalc:u2|VgaInterface:u1|hs_p at LC_X10_Y13_N5
--operation mode is normal

D1_hs_p_lut_out = !D1_vector_x[8] & (D1_vector_x[7] & !D1L27);
D1_hs_p = DFFEAS(D1_hs_p_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , , , , , );


--D1_vs_p is vgaCalc:u2|VgaInterface:u1|vs_p at LC_X14_Y13_N5
--operation mode is normal

D1_vs_p_lut_out = !D1L47 & D1L611 & D1_vector_y[3] & !D1_vector_y[4];
D1_vs_p = DFFEAS(D1_vs_p_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , , , , , );


--H1_ram_block1a1 is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|ram_block1a1 at M4K_X17_Y14
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
H1_ram_block1a1_PORT_A_address = BUS(D1_char_address[0], D1_char_address[1], D1_char_address[2], D1_char_address[3], D1_char_address[4], D1_char_address[5], D1_char_address[6], D1_char_address[7], D1_char_address[8], D1_char_address[9], D1_char_address[10], D1_char_address[11]);
H1_ram_block1a1_PORT_A_address_reg = DFFE(H1_ram_block1a1_PORT_A_address, H1_ram_block1a1_clock_0, , , );
H1_ram_block1a1_clock_0 = GLOBAL(D1_clk);
H1_ram_block1a1_PORT_A_data_out = MEMORY(, , H1_ram_block1a1_PORT_A_address_reg, , , , , , H1_ram_block1a1_clock_0, , , , , );
H1_ram_block1a1_PORT_A_data_out_reg = DFFE(H1_ram_block1a1_PORT_A_data_out, H1_ram_block1a1_clock_0, , , );
H1_ram_block1a1 = H1_ram_block1a1_PORT_A_data_out_reg[0];


--H1_ram_block1a2 is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|ram_block1a2 at M4K_X17_Y15
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
H1_ram_block1a2_PORT_A_address = BUS(D1_char_address[0], D1_char_address[1], D1_char_address[2], D1_char_address[3], D1_char_address[4], D1_char_address[5], D1_char_address[6], D1_char_address[7], D1_char_address[8], D1_char_address[9], D1_char_address[10], D1_char_address[11]);
H1_ram_block1a2_PORT_A_address_reg = DFFE(H1_ram_block1a2_PORT_A_address, H1_ram_block1a2_clock_0, , , );
H1_ram_block1a2_clock_0 = GLOBAL(D1_clk);
H1_ram_block1a2_PORT_A_data_out = MEMORY(, , H1_ram_block1a2_PORT_A_address_reg, , , , , , H1_ram_block1a2_clock_0, , , , , );
H1_ram_block1a2_PORT_A_data_out_reg = DFFE(H1_ram_block1a2_PORT_A_data_out, H1_ram_block1a2_clock_0, , , );
H1_ram_block1a2 = H1_ram_block1a2_PORT_A_data_out_reg[0];


--H1_ram_block1a0 is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|ram_block1a0 at M4K_X17_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
H1_ram_block1a0_PORT_A_address = BUS(D1_char_address[0], D1_char_address[1], D1_char_address[2], D1_char_address[3], D1_char_address[4], D1_char_address[5], D1_char_address[6], D1_char_address[7], D1_char_address[8], D1_char_address[9], D1_char_address[10], D1_char_address[11]);
H1_ram_block1a0_PORT_A_address_reg = DFFE(H1_ram_block1a0_PORT_A_address, H1_ram_block1a0_clock_0, , , );
H1_ram_block1a0_clock_0 = GLOBAL(D1_clk);
H1_ram_block1a0_PORT_A_data_out = MEMORY(, , H1_ram_block1a0_PORT_A_address_reg, , , , , , H1_ram_block1a0_clock_0, , , , , );
H1_ram_block1a0_PORT_A_data_out_reg = DFFE(H1_ram_block1a0_PORT_A_data_out, H1_ram_block1a0_clock_0, , , );
H1_ram_block1a0 = H1_ram_block1a0_PORT_A_data_out_reg[0];


--J1L1 is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|mux_gcb:mux2|w_result148w~44 at LC_X16_Y13_N2
--operation mode is normal

H1_address_reg_a[5]_qfbk = H1_address_reg_a[5];
J1L1 = H1_address_reg_a[4] & (H1_address_reg_a[5]_qfbk) # !H1_address_reg_a[4] & (H1_address_reg_a[5]_qfbk & (H1_ram_block1a2) # !H1_address_reg_a[5]_qfbk & H1_ram_block1a0);

--H1_address_reg_a[5] is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|address_reg_a[5] at LC_X16_Y13_N2
--operation mode is normal

H1_address_reg_a[5] = DFFEAS(J1L1, GLOBAL(D1_clk), VCC, , , H1_address_reg_a[1], , , VCC);


--H1_ram_block1a3 is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|ram_block1a3 at M4K_X17_Y13
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
H1_ram_block1a3_PORT_A_address = BUS(D1_char_address[0], D1_char_address[1], D1_char_address[2], D1_char_address[3], D1_char_address[4], D1_char_address[5], D1_char_address[6], D1_char_address[7], D1_char_address[8], D1_char_address[9], D1_char_address[10], D1_char_address[11]);
H1_ram_block1a3_PORT_A_address_reg = DFFE(H1_ram_block1a3_PORT_A_address, H1_ram_block1a3_clock_0, , , );
H1_ram_block1a3_clock_0 = GLOBAL(D1_clk);
H1_ram_block1a3_PORT_A_data_out = MEMORY(, , H1_ram_block1a3_PORT_A_address_reg, , , , , , H1_ram_block1a3_clock_0, , , , , );
H1_ram_block1a3_PORT_A_data_out_reg = DFFE(H1_ram_block1a3_PORT_A_data_out, H1_ram_block1a3_clock_0, , , );
H1_ram_block1a3 = H1_ram_block1a3_PORT_A_data_out_reg[0];


--J1L2 is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|mux_gcb:mux2|w_result148w~45 at LC_X14_Y13_N9
--operation mode is normal

H1_address_reg_a[4]_qfbk = H1_address_reg_a[4];
J1L2 = H1_address_reg_a[4]_qfbk & (J1L1 & (H1_ram_block1a3) # !J1L1 & H1_ram_block1a1) # !H1_address_reg_a[4]_qfbk & (J1L1);

--H1_address_reg_a[4] is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|address_reg_a[4] at LC_X14_Y13_N9
--operation mode is normal

H1_address_reg_a[4] = DFFEAS(J1L2, GLOBAL(D1_clk), VCC, , , H1_address_reg_a[0], , , VCC);


--D1_en is vgaCalc:u2|VgaInterface:u1|en at LC_X13_Y15_N4
--operation mode is normal

D1_en_lut_out = D1_char_address[12] & D1_char_address[13] & D1_char_address[11] & D1_char_address[10];
D1_en = DFFEAS(D1_en_lut_out, GLOBAL(D1_clk), VCC, , , , , , );


--D1_vector_y[5] is vgaCalc:u2|VgaInterface:u1|vector_y[5] at LC_X13_Y13_N5
--operation mode is arithmetic

D1_vector_y[5]_carry_eqn = (!D1L301 & GND) # (D1L301 & VCC);
D1_vector_y[5]_lut_out = D1_vector_y[5] $ D1_vector_y[5]_carry_eqn;
D1_vector_y[5] = DFFEAS(D1_vector_y[5]_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , D1L77, , , , );

--D1L701 is vgaCalc:u2|VgaInterface:u1|vector_y[5]~220 at LC_X13_Y13_N5
--operation mode is arithmetic

D1L701_cout_0 = !D1L301 # !D1_vector_y[5];
D1L701 = CARRY(D1L701_cout_0);

--D1L801 is vgaCalc:u2|VgaInterface:u1|vector_y[5]~220COUT1_260 at LC_X13_Y13_N5
--operation mode is arithmetic

D1L801_cout_1 = !D1L301 # !D1_vector_y[5];
D1L801 = CARRY(D1L801_cout_1);


--D1_vector_y[6] is vgaCalc:u2|VgaInterface:u1|vector_y[6] at LC_X13_Y13_N6
--operation mode is arithmetic

D1_vector_y[6]_carry_eqn = (!D1L301 & D1L701) # (D1L301 & D1L801);
D1_vector_y[6]_lut_out = D1_vector_y[6] $ (!D1_vector_y[6]_carry_eqn);
D1_vector_y[6] = DFFEAS(D1_vector_y[6]_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , D1L77, , , , );

--D1L011 is vgaCalc:u2|VgaInterface:u1|vector_y[6]~224 at LC_X13_Y13_N6
--operation mode is arithmetic

D1L011_cout_0 = D1_vector_y[6] & (!D1L701);
D1L011 = CARRY(D1L011_cout_0);

--D1L111 is vgaCalc:u2|VgaInterface:u1|vector_y[6]~224COUT1_261 at LC_X13_Y13_N6
--operation mode is arithmetic

D1L111_cout_1 = D1_vector_y[6] & (!D1L801);
D1L111 = CARRY(D1L111_cout_1);


--D1_vector_y[7] is vgaCalc:u2|VgaInterface:u1|vector_y[7] at LC_X13_Y13_N7
--operation mode is arithmetic

D1_vector_y[7]_carry_eqn = (!D1L301 & D1L011) # (D1L301 & D1L111);
D1_vector_y[7]_lut_out = D1_vector_y[7] $ (D1_vector_y[7]_carry_eqn);
D1_vector_y[7] = DFFEAS(D1_vector_y[7]_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , D1L77, , , , );

--D1L311 is vgaCalc:u2|VgaInterface:u1|vector_y[7]~228 at LC_X13_Y13_N7
--operation mode is arithmetic

D1L311_cout_0 = !D1L011 # !D1_vector_y[7];
D1L311 = CARRY(D1L311_cout_0);

--D1L411 is vgaCalc:u2|VgaInterface:u1|vector_y[7]~228COUT1_262 at LC_X13_Y13_N7
--operation mode is arithmetic

D1L411_cout_1 = !D1L111 # !D1_vector_y[7];
D1L411 = CARRY(D1L411_cout_1);


--D1_vector_y[8] is vgaCalc:u2|VgaInterface:u1|vector_y[8] at LC_X13_Y13_N8
--operation mode is normal

D1_vector_y[8]_carry_eqn = (!D1L301 & D1L311) # (D1L301 & D1L411);
D1_vector_y[8]_lut_out = D1_vector_y[8] $ !D1_vector_y[8]_carry_eqn;
D1_vector_y[8] = DFFEAS(D1_vector_y[8]_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , D1L77, , , , );


--D1L611 is vgaCalc:u2|VgaInterface:u1|vector_y[8]~235 at LC_X14_Y13_N0
--operation mode is normal

D1L611 = D1_vector_y[6] & D1_vector_y[5] & D1_vector_y[8] & D1_vector_y[7];


--D1_vector_x[9] is vgaCalc:u2|VgaInterface:u1|vector_x[9] at LC_X10_Y13_N2
--operation mode is normal

D1_vector_x[9]_lut_out = D1L1 & (!D1L77);
D1_vector_x[9] = DFFEAS(D1_vector_x[9]_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , , , , , );


--D1_vector_x[8] is vgaCalc:u2|VgaInterface:u1|vector_x[8] at LC_X11_Y13_N5
--operation mode is normal

D1_vector_x[8]_lut_out = D1L2 & (!D1L77);
D1_vector_x[8] = DFFEAS(D1_vector_x[8]_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , , , , , );


--D1L06 is vgaCalc:u2|VgaInterface:u1|LessThan~1666 at LC_X11_Y13_N0
--operation mode is normal

D1_vector_x[7]_qfbk = D1_vector_x[7];
D1L06 = D1_vector_x[7]_qfbk # D1_vector_x[8];

--D1_vector_x[7] is vgaCalc:u2|VgaInterface:u1|vector_x[7] at LC_X11_Y13_N0
--operation mode is normal

D1_vector_x[7] = DFFEAS(D1L06, GLOBAL(D1_clk), !GLOBAL(reset), , , D1L5, , , VCC);


--D1_vector_x[5] is vgaCalc:u2|VgaInterface:u1|vector_x[5] at LC_X11_Y13_N9
--operation mode is normal

D1_vector_x[5]_lut_out = D1L31 & (!D1L77);
D1_vector_x[5] = DFFEAS(D1_vector_x[5]_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , , , , , );


--D1L27 is vgaCalc:u2|VgaInterface:u1|process6~29 at LC_X10_Y13_N6
--operation mode is normal

D1L27 = D1_vector_x[6] & D1_vector_x[5] & D1_vector_x[4] # !D1_vector_x[6] & !D1_vector_x[5] & !D1_vector_x[4] # !D1_vector_x[9];


--D1_vector_y[4] is vgaCalc:u2|VgaInterface:u1|vector_y[4] at LC_X13_Y13_N4
--operation mode is arithmetic

D1_vector_y[4]_lut_out = D1_vector_y[4] $ !D1L001;
D1_vector_y[4] = DFFEAS(D1_vector_y[4]_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , D1L77, , , , );

--D1L301 is vgaCalc:u2|VgaInterface:u1|vector_y[4]~237 at LC_X13_Y13_N4
--operation mode is arithmetic

D1L301 = D1L401;


--D1_vector_y[2] is vgaCalc:u2|VgaInterface:u1|vector_y[2] at LC_X13_Y13_N2
--operation mode is arithmetic

D1_vector_y[2]_lut_out = D1_vector_y[2] $ (!D1L49);
D1_vector_y[2] = DFFEAS(D1_vector_y[2]_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , D1L77, , , , );

--D1L79 is vgaCalc:u2|VgaInterface:u1|vector_y[2]~241 at LC_X13_Y13_N2
--operation mode is arithmetic

D1L79_cout_0 = D1_vector_y[2] & (!D1L49);
D1L79 = CARRY(D1L79_cout_0);

--D1L89 is vgaCalc:u2|VgaInterface:u1|vector_y[2]~241COUT1_259 at LC_X13_Y13_N2
--operation mode is arithmetic

D1L89_cout_1 = D1_vector_y[2] & (!D1L59);
D1L89 = CARRY(D1L89_cout_1);


--D1_vector_y[1] is vgaCalc:u2|VgaInterface:u1|vector_y[1] at LC_X13_Y13_N1
--operation mode is arithmetic

D1_vector_y[1]_lut_out = D1_vector_y[1] $ (D1L19);
D1_vector_y[1] = DFFEAS(D1_vector_y[1]_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , D1L77, , , , );

--D1L49 is vgaCalc:u2|VgaInterface:u1|vector_y[1]~245 at LC_X13_Y13_N1
--operation mode is arithmetic

D1L49_cout_0 = !D1L19 # !D1_vector_y[1];
D1L49 = CARRY(D1L49_cout_0);

--D1L59 is vgaCalc:u2|VgaInterface:u1|vector_y[1]~245COUT1_258 at LC_X13_Y13_N1
--operation mode is arithmetic

D1L59_cout_1 = !D1L29 # !D1_vector_y[1];
D1L59 = CARRY(D1L59_cout_1);


--D1L47 is vgaCalc:u2|VgaInterface:u1|process7~33 at LC_X14_Y13_N2
--operation mode is normal

D1L47 = D1_vector_y[2] # !D1_vector_y[1];


--D1_vector_y[3] is vgaCalc:u2|VgaInterface:u1|vector_y[3] at LC_X13_Y13_N3
--operation mode is arithmetic

D1_vector_y[3]_lut_out = D1_vector_y[3] $ D1L79;
D1_vector_y[3] = DFFEAS(D1_vector_y[3]_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , D1L77, , , , );

--D1L001 is vgaCalc:u2|VgaInterface:u1|vector_y[3]~249 at LC_X13_Y13_N3
--operation mode is arithmetic

D1L001_cout_0 = !D1L79 # !D1_vector_y[3];
D1L001 = CARRY(D1L001_cout_0);

--D1L101 is vgaCalc:u2|VgaInterface:u1|vector_y[3]~249COUT1 at LC_X13_Y13_N3
--operation mode is arithmetic

D1L101_cout_1 = !D1L89 # !D1_vector_y[3];
D1L101 = CARRY(D1L101_cout_1);


--D1_char_address[0] is vgaCalc:u2|VgaInterface:u1|char_address[0] at LC_X15_Y13_N2
--operation mode is normal

D1_char_address[0]_lut_out = D1_vector_x[0] & (D1L34 # !D1L54);
D1_char_address[0] = DFFEAS(D1_char_address[0]_lut_out, GLOBAL(D1_clk), VCC, , , , , , );


--D1_char_address[1] is vgaCalc:u2|VgaInterface:u1|char_address[1] at LC_X15_Y13_N5
--operation mode is normal

D1_char_address[1]_lut_out = D1_vector_x[1] & (D1L34 # !D1L54);
D1_char_address[1] = DFFEAS(D1_char_address[1]_lut_out, GLOBAL(D1_clk), VCC, , , , , , );


--D1_char_address[2] is vgaCalc:u2|VgaInterface:u1|char_address[2] at LC_X15_Y13_N8
--operation mode is normal

D1_char_address[2]_lut_out = D1_vector_x[2] & (D1L34 # !D1L54);
D1_char_address[2] = DFFEAS(D1_char_address[2]_lut_out, GLOBAL(D1_clk), VCC, , , , , , );


--D1_char_address[3] is vgaCalc:u2|VgaInterface:u1|char_address[3] at LC_X15_Y13_N3
--operation mode is normal

D1_char_address[3]_lut_out = D1_vector_x[3] & (D1L34 # !D1L54);
D1_char_address[3] = DFFEAS(D1_char_address[3]_lut_out, GLOBAL(D1_clk), VCC, , , , , , );


--D1_char_address[4] is vgaCalc:u2|VgaInterface:u1|char_address[4] at LC_X15_Y13_N4
--operation mode is normal

D1_char_address[4]_lut_out = D1_vector_x[4] & (D1L34 # !D1L54);
D1_char_address[4] = DFFEAS(D1_char_address[4]_lut_out, GLOBAL(D1_clk), VCC, , , , , , );


--D1_char_address[5] is vgaCalc:u2|VgaInterface:u1|char_address[5] at LC_X15_Y13_N6
--operation mode is normal

D1_char_address[5]_lut_out = D1_vector_y[0] & (D1L34 # !D1L54);
D1_char_address[5] = DFFEAS(D1_char_address[5]_lut_out, GLOBAL(D1_clk), VCC, , , , , , );


--D1_char_address[6] is vgaCalc:u2|VgaInterface:u1|char_address[6] at LC_X15_Y13_N1
--operation mode is normal

D1_char_address[6]_lut_out = D1_vector_y[1] & (D1L34 # !D1L54);
D1_char_address[6] = DFFEAS(D1_char_address[6]_lut_out, GLOBAL(D1_clk), VCC, , , , , , );


--D1_char_address[7] is vgaCalc:u2|VgaInterface:u1|char_address[7] at LC_X13_Y13_N9
--operation mode is normal

D1_char_address[7]_lut_out = D1_vector_y[2] & (D1L34 # !D1L54);
D1_char_address[7] = DFFEAS(D1_char_address[7]_lut_out, GLOBAL(D1_clk), VCC, , , , , , );


--D1_char_address[8] is vgaCalc:u2|VgaInterface:u1|char_address[8] at LC_X14_Y13_N4
--operation mode is normal

D1_char_address[8]_lut_out = D1_vector_y[3] & (D1L34 # !D1L54);
D1_char_address[8] = DFFEAS(D1_char_address[8]_lut_out, GLOBAL(D1_clk), VCC, , , , , , );


--D1_char_address[9] is vgaCalc:u2|VgaInterface:u1|char_address[9] at LC_X14_Y13_N1
--operation mode is normal

D1_char_address[9]_lut_out = D1_vector_y[4] & (D1L34 # !D1L54);
D1_char_address[9] = DFFEAS(D1_char_address[9]_lut_out, GLOBAL(D1_clk), VCC, , , , , , );


--D1_char_address[10] is vgaCalc:u2|VgaInterface:u1|char_address[10] at LC_X13_Y15_N1
--operation mode is normal

D1_char_address[10]_lut_out = D1L07 & (D1_vga_data[16]) # !D1L07 & D1L94;
D1_char_address[10] = DFFEAS(D1_char_address[10]_lut_out, GLOBAL(D1_clk), VCC, , , D1_vga_data[20], , D1L74, D1L17);


--D1_char_address[11] is vgaCalc:u2|VgaInterface:u1|char_address[11] at LC_X13_Y15_N8
--operation mode is normal

D1_char_address[11]_lut_out = D1L07 & (D1_vga_data[4]) # !D1L07 & D1L15;
D1_char_address[11] = DFFEAS(D1_char_address[11]_lut_out, GLOBAL(D1_clk), VCC, , , D1_vga_data[21], , D1L74, D1L17);


--H1_address_reg_a[0] is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|address_reg_a[0] at LC_X13_Y12_N2
--operation mode is normal

H1_address_reg_a[0]_lut_out = D1_char_address[12];
H1_address_reg_a[0] = DFFEAS(H1_address_reg_a[0]_lut_out, GLOBAL(D1_clk), VCC, , , , , , );


--H1_address_reg_a[1] is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|address_reg_a[1] at LC_X16_Y13_N4
--operation mode is normal

H1_address_reg_a[1]_lut_out = GND;
H1_address_reg_a[1] = DFFEAS(H1_address_reg_a[1]_lut_out, GLOBAL(D1_clk), VCC, , , D1_char_address[13], , , VCC);


--D1_char_address[13] is vgaCalc:u2|VgaInterface:u1|char_address[13] at LC_X12_Y13_N5
--operation mode is normal

D1_char_address[13]_lut_out = D1L07 & (D1_vga_data[4]) # !D1L07 & D1L35;
D1_char_address[13] = DFFEAS(D1_char_address[13]_lut_out, GLOBAL(D1_clk), VCC, , , D1_vga_data[23], , D1L74, D1L17);


--D1_char_address[12] is vgaCalc:u2|VgaInterface:u1|char_address[12] at LC_X13_Y15_N7
--operation mode is normal

D1_char_address[12]_lut_out = D1L07 & (D1_vga_data[18]) # !D1L07 & D1L55;
D1_char_address[12] = DFFEAS(D1_char_address[12]_lut_out, GLOBAL(D1_clk), VCC, , , D1_vga_data[22], , D1L74, D1L17);


--D1L57 is vgaCalc:u2|VgaInterface:u1|reduce_nor~73 at LC_X11_Y13_N3
--operation mode is normal

D1L57 = D1_vector_x[5] # D1_vector_x[6] # !D1_vector_x[9] # !D1_vector_x[8];


--D1_vector_x[3] is vgaCalc:u2|VgaInterface:u1|vector_x[3] at LC_X15_Y13_N7
--operation mode is normal

D1_vector_x[3]_lut_out = D1L61;
D1_vector_x[3] = DFFEAS(D1_vector_x[3]_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , , , , , );


--D1_vector_x[2] is vgaCalc:u2|VgaInterface:u1|vector_x[2] at LC_X15_Y13_N9
--operation mode is normal

D1_vector_x[2]_lut_out = GND;
D1_vector_x[2] = DFFEAS(D1_vector_x[2]_lut_out, GLOBAL(D1_clk), !GLOBAL(reset), , , D1L91, , , VCC);


--D1L67 is vgaCalc:u2|VgaInterface:u1|reduce_nor~74 at LC_X11_Y13_N1
--operation mode is normal