subadd.vhd

用VHDL写的一个小游戏

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--实验题号   : Ex2-3
--项目名称   : 一位十进制加减法运算器
--文件名     : SubAdd.vhd
--作者       : 田甲
--班号.      : 计45 
--创建日期   : 2006-03-23
--目标芯片   : EP1C6Q240C8
--电路模式   : 模式1
--时钟选择   : 
--演示说明   : 用按键1、2分别输入SAb、SAa，用数显管D2和D1分别表示加数SAa和被加（减）数SAb
--			   用按键7输入加减号，0表示加号用数显管D6和D5分别表示和sum的高位和低位				
--功能描述   : 本文件给出了一位十进制加减法运算器的结构描述，调用了4bit加法器和4bit减法器，涉及port map等语法现象。
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library ieee;
use ieee.std_logic_1164.all;

entity SubAdd is
port(SAa, SAb: in std_logic_vector(3 downto 0);
    operator: in std_logic;
    sum: out std_logic_vector(7 downto 0) );
end entity;

architecture Impl of SubAdd is
component BCD4Adder is
port(BCDa, BCDb: in std_logic_vector(3 downto 0);
    BCDs: out std_logic_vector(3 downto 0);
    BCDcarry: out std_logic );
end component;

component FourBitSuber is
port(Sa, Sb: in std_logic_vector(3 downto 0);
    Ss: out std_logic_vector(3 downto 0);
    Ssgn: out std_logic );
end component;

signal high, low, tmp1, tmp2:std_logic_vector(3 downto 0);
signal zero:std_logic:='0';
signal tmpc1, tmpc2:std_logic;
begin
ua: BCD4Adder port map
    (BCDa=>SAa, BCDb=>SAb, BCDs=>tmp1, BCDcarry=>tmpc1);
us: FourBitSuber port map
	(Sa=>SAa, Sb=>SAb, Ss=>tmp2, Ssgn=>tmpc2); 
high(3)<=operator and tmpc2;
high(2)<=operator and tmpc2;
high(1)<=operator and tmpc2;
high(0)<=(not operator) and tmpc1;
low(3)<=(operator and tmp2(3))or((not operator)and tmp1(3));
low(2)<=(operator and tmp2(2))or((not operator)and tmp1(2));
low(1)<=(operator and tmp2(1))or((not operator)and tmp1(1));
low(0)<=(operator and tmp2(0))or((not operator)and tmp1(0));
sum(7 downto 4)<=high;
sum(3 downto 0)<=low;
end architecture Impl;