readkey.vhd

用VHDL写的一个小游戏

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--实验题号   : Ex5-1
--项目名称   : 键盘信号处理器
--文件名     : Readkey.vhd
--作者       : 田甲
--班号.      : 计45 
--创建日期   : 2006-05-25
--目标芯片   : EP1C6Q240C8
--电路模式   : 模式5
--功能描述   : 本文件给出了键盘信号处理器的结构描述
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Readkey is
port(clk, clk_50m, ps2data: IN STD_LOGIC; 
  		feedback             :         out STD_LOGIC;
  		key                  :         out STD_LOGIC_VECTOR(7 downto 0)
        );
end entity;

architecture behave of Readkey is
signal ps_data, ps_clk		:std_logic;
signal clk_6m				:std_logic:='0';
signal counter				:std_logic_vector(1 downto 0); 
signal stat					:std_logic_vector(3 downto 0):="0000";
signal tempcode				:std_logic_vector(7 downto 0);
signal flag,tempenable		:std_logic:='0';

begin
	key<=tempcode;
	feedback<=tempenable;
	
	
	process(clk_50m)
	begin
		if clk_50m'event and clk_50m='1' then
			counter<=counter+1;
			if counter="00" then
				clk_6m<=not clk_6m;
			end if;
		end if;
	end process;
	
	process(clk_6m)
	begin
		if clk_6m'event and clk_6m='1' then
			ps_clk<=clk;
			ps_data<=ps2data;
		end if;
	end process;
	
	process(ps_clk)
	begin
		if ps_clk'event and ps_clk='0' then
			stat<=stat+1;
			if stat=0 then
			elsif stat=1 then
				tempcode(0)<=ps_data;
			elsif stat=2 then
				tempcode(1)<=ps_data;
			elsif stat=3 then
				tempcode(2)<=ps_data;
			elsif stat=4 then
				tempcode(3)<=ps_data;
			elsif stat=5 then
				tempcode(4)<=ps_data;
			elsif stat=6 then
				tempcode(5)<=ps_data;
			elsif stat=7 then
				tempcode(6)<=ps_data;
			elsif stat=8 then
				tempcode(7)<=ps_data;
			elsif stat=9 then
				tempenable<='1';
			elsif stat=10 then
				stat<="0000";
				tempenable<='0';
			end if;
		end if;
	end process;
					
end architecture behave;