vgaps2.map.eqn

用VHDL写的一个小游戏

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--D1_pod_vga_r is vgaCalc:u2|VgaInterface:u1|pod_vga_r
--operation mode is normal

D1_pod_vga_r_lut_out = D1_vga_r & D1_enable;
D1_pod_vga_r = DFFEAS(D1_pod_vga_r_lut_out, D1_clk, !reset, , , , , , );


--D1_poc_vga_hs is vgaCalc:u2|VgaInterface:u1|poc_vga_hs
--operation mode is normal

D1_poc_vga_hs_lut_out = !D1_hs_p;
D1_poc_vga_hs = DFFEAS(D1_poc_vga_hs_lut_out, D1_clk, !reset, , , , , , );


--D1_poc_vga_vs is vgaCalc:u2|VgaInterface:u1|poc_vga_vs
--operation mode is normal

D1_poc_vga_vs_lut_out = !D1_vs_p;
D1_poc_vga_vs = DFFEAS(D1_poc_vga_vs_lut_out, D1_clk, !reset, , , , , , );


--D1_vga_r is vgaCalc:u2|VgaInterface:u1|vga_r
--operation mode is normal

D1_vga_r_lut_out = J1L2 & (!D1_en);
D1_vga_r = DFFEAS(D1_vga_r_lut_out, D1_clk, VCC, , , , , , );


--D1_enable is vgaCalc:u2|VgaInterface:u1|enable
--operation mode is normal

D1_enable_lut_out = !D1L99 & (!D1_vector_x[8] & !D1_vector_x[7] # !D1_vector_x[9]);
D1_enable = DFFEAS(D1_enable_lut_out, D1_clk, VCC, , , , , , );


--D1_clk is vgaCalc:u2|VgaInterface:u1|clk
--operation mode is normal

D1_clk_lut_out = !D1_clk;
D1_clk = DFFEAS(D1_clk_lut_out, clk50m, VCC, , , , , , );


--D1_hs_p is vgaCalc:u2|VgaInterface:u1|hs_p
--operation mode is normal

D1_hs_p_lut_out = !D1_vector_x[8] & !D1L46 & (D1_vector_x[7]);
D1_hs_p = DFFEAS(D1_hs_p_lut_out, D1_clk, !reset, , , , , , );


--D1_vs_p is vgaCalc:u2|VgaInterface:u1|vs_p
--operation mode is normal

D1_vs_p_lut_out = !D1_vector_y[4] & !D1L66 & D1_vector_y[3] & D1L99;
D1_vs_p = DFFEAS(D1_vs_p_lut_out, D1_clk, !reset, , , , , , );


--H1_ram_block1a1 is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|ram_block1a1
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
H1_ram_block1a1_PORT_A_address = BUS(D1_char_address[0], D1_char_address[1], D1_char_address[2], D1_char_address[3], D1_char_address[4], D1_char_address[5], D1_char_address[6], D1_char_address[7], D1_char_address[8], D1_char_address[9], D1_char_address[10], D1_char_address[11]);
H1_ram_block1a1_PORT_A_address_reg = DFFE(H1_ram_block1a1_PORT_A_address, H1_ram_block1a1_clock_0, , , );
H1_ram_block1a1_clock_0 = D1_clk;
H1_ram_block1a1_PORT_A_data_out = MEMORY(, , H1_ram_block1a1_PORT_A_address_reg, , , , , , H1_ram_block1a1_clock_0, , , , , );
H1_ram_block1a1_PORT_A_data_out_reg = DFFE(H1_ram_block1a1_PORT_A_data_out, H1_ram_block1a1_clock_0, , , );
H1_ram_block1a1 = H1_ram_block1a1_PORT_A_data_out_reg[0];


--H1_address_reg_a[4] is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|address_reg_a[4]
--operation mode is normal

H1_address_reg_a[4]_lut_out = H1_address_reg_a[0];
H1_address_reg_a[4] = DFFEAS(H1_address_reg_a[4]_lut_out, D1_clk, VCC, , , , , , );


--H1_ram_block1a2 is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|ram_block1a2
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
H1_ram_block1a2_PORT_A_address = BUS(D1_char_address[0], D1_char_address[1], D1_char_address[2], D1_char_address[3], D1_char_address[4], D1_char_address[5], D1_char_address[6], D1_char_address[7], D1_char_address[8], D1_char_address[9], D1_char_address[10], D1_char_address[11]);
H1_ram_block1a2_PORT_A_address_reg = DFFE(H1_ram_block1a2_PORT_A_address, H1_ram_block1a2_clock_0, , , );
H1_ram_block1a2_clock_0 = D1_clk;
H1_ram_block1a2_PORT_A_data_out = MEMORY(, , H1_ram_block1a2_PORT_A_address_reg, , , , , , H1_ram_block1a2_clock_0, , , , , );
H1_ram_block1a2_PORT_A_data_out_reg = DFFE(H1_ram_block1a2_PORT_A_data_out, H1_ram_block1a2_clock_0, , , );
H1_ram_block1a2 = H1_ram_block1a2_PORT_A_data_out_reg[0];


--H1_address_reg_a[5] is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|address_reg_a[5]
--operation mode is normal

H1_address_reg_a[5]_lut_out = H1_address_reg_a[1];
H1_address_reg_a[5] = DFFEAS(H1_address_reg_a[5]_lut_out, D1_clk, VCC, , , , , , );


--H1_ram_block1a0 is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|ram_block1a0
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
H1_ram_block1a0_PORT_A_address = BUS(D1_char_address[0], D1_char_address[1], D1_char_address[2], D1_char_address[3], D1_char_address[4], D1_char_address[5], D1_char_address[6], D1_char_address[7], D1_char_address[8], D1_char_address[9], D1_char_address[10], D1_char_address[11]);
H1_ram_block1a0_PORT_A_address_reg = DFFE(H1_ram_block1a0_PORT_A_address, H1_ram_block1a0_clock_0, , , );
H1_ram_block1a0_clock_0 = D1_clk;
H1_ram_block1a0_PORT_A_data_out = MEMORY(, , H1_ram_block1a0_PORT_A_address_reg, , , , , , H1_ram_block1a0_clock_0, , , , , );
H1_ram_block1a0_PORT_A_data_out_reg = DFFE(H1_ram_block1a0_PORT_A_data_out, H1_ram_block1a0_clock_0, , , );
H1_ram_block1a0 = H1_ram_block1a0_PORT_A_data_out_reg[0];


--J1L1 is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|mux_gcb:mux2|w_result148w~44
--operation mode is normal

J1L1 = H1_address_reg_a[4] & (H1_address_reg_a[5]) # !H1_address_reg_a[4] & (H1_address_reg_a[5] & H1_ram_block1a2 # !H1_address_reg_a[5] & (H1_ram_block1a0));


--H1_ram_block1a3 is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|ram_block1a3
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
H1_ram_block1a3_PORT_A_address = BUS(D1_char_address[0], D1_char_address[1], D1_char_address[2], D1_char_address[3], D1_char_address[4], D1_char_address[5], D1_char_address[6], D1_char_address[7], D1_char_address[8], D1_char_address[9], D1_char_address[10], D1_char_address[11]);
H1_ram_block1a3_PORT_A_address_reg = DFFE(H1_ram_block1a3_PORT_A_address, H1_ram_block1a3_clock_0, , , );
H1_ram_block1a3_clock_0 = D1_clk;
H1_ram_block1a3_PORT_A_data_out = MEMORY(, , H1_ram_block1a3_PORT_A_address_reg, , , , , , H1_ram_block1a3_clock_0, , , , , );
H1_ram_block1a3_PORT_A_data_out_reg = DFFE(H1_ram_block1a3_PORT_A_data_out, H1_ram_block1a3_clock_0, , , );
H1_ram_block1a3 = H1_ram_block1a3_PORT_A_data_out_reg[0];


--J1L2 is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|mux_gcb:mux2|w_result148w~45
--operation mode is normal

J1L2 = H1_address_reg_a[4] & (J1L1 & (H1_ram_block1a3) # !J1L1 & H1_ram_block1a1) # !H1_address_reg_a[4] & (J1L1);


--D1_en is vgaCalc:u2|VgaInterface:u1|en
--operation mode is normal

D1_en_lut_out = D1_char_address[10] & D1_char_address[11] & D1_char_address[13] & D1_char_address[12];
D1_en = DFFEAS(D1_en_lut_out, D1_clk, VCC, , , , , , );


--D1_vector_y[5] is vgaCalc:u2|VgaInterface:u1|vector_y[5]
--operation mode is arithmetic

D1_vector_y[5]_carry_eqn = D1L19;
D1_vector_y[5]_lut_out = D1_vector_y[5] $ (D1_vector_y[5]_carry_eqn);
D1_vector_y[5] = DFFEAS(D1_vector_y[5]_lut_out, D1_clk, !reset, , D1L96, , , , );

--D1L39 is vgaCalc:u2|VgaInterface:u1|vector_y[5]~220
--operation mode is arithmetic

D1L39 = CARRY(!D1L19 # !D1_vector_y[5]);


--D1_vector_y[6] is vgaCalc:u2|VgaInterface:u1|vector_y[6]
--operation mode is arithmetic

D1_vector_y[6]_carry_eqn = D1L39;
D1_vector_y[6]_lut_out = D1_vector_y[6] $ (!D1_vector_y[6]_carry_eqn);
D1_vector_y[6] = DFFEAS(D1_vector_y[6]_lut_out, D1_clk, !reset, , D1L96, , , , );

--D1L59 is vgaCalc:u2|VgaInterface:u1|vector_y[6]~224
--operation mode is arithmetic

D1L59 = CARRY(D1_vector_y[6] & (!D1L39));


--D1_vector_y[7] is vgaCalc:u2|VgaInterface:u1|vector_y[7]
--operation mode is arithmetic

D1_vector_y[7]_carry_eqn = D1L59;
D1_vector_y[7]_lut_out = D1_vector_y[7] $ (D1_vector_y[7]_carry_eqn);
D1_vector_y[7] = DFFEAS(D1_vector_y[7]_lut_out, D1_clk, !reset, , D1L96, , , , );

--D1L79 is vgaCalc:u2|VgaInterface:u1|vector_y[7]~228
--operation mode is arithmetic

D1L79 = CARRY(!D1L59 # !D1_vector_y[7]);


--D1_vector_y[8] is vgaCalc:u2|VgaInterface:u1|vector_y[8]
--operation mode is normal

D1_vector_y[8]_carry_eqn = D1L79;
D1_vector_y[8]_lut_out = D1_vector_y[8] $ (!D1_vector_y[8]_carry_eqn);
D1_vector_y[8] = DFFEAS(D1_vector_y[8]_lut_out, D1_clk, !reset, , D1L96, , , , );


--D1L99 is vgaCalc:u2|VgaInterface:u1|vector_y[8]~235
--operation mode is normal

D1L99 = D1_vector_y[5] & D1_vector_y[6] & D1_vector_y[7] & D1_vector_y[8];


--D1_vector_x[9] is vgaCalc:u2|VgaInterface:u1|vector_x[9]
--operation mode is normal

D1_vector_x[9]_lut_out = D1L1 & !D1L96;
D1_vector_x[9] = DFFEAS(D1_vector_x[9]_lut_out, D1_clk, !reset, , , , , , );


--D1_vector_x[8] is vgaCalc:u2|VgaInterface:u1|vector_x[8]
--operation mode is normal

D1_vector_x[8]_lut_out = D1L2 & !D1L96;
D1_vector_x[8] = DFFEAS(D1_vector_x[8]_lut_out, D1_clk, !reset, , , , , , );


--D1_vector_x[7] is vgaCalc:u2|VgaInterface:u1|vector_x[7]
--operation mode is normal

D1_vector_x[7]_lut_out = D1L4;
D1_vector_x[7] = DFFEAS(D1_vector_x[7]_lut_out, D1_clk, !reset, , , , , , );


--D1L25 is vgaCalc:u2|VgaInterface:u1|LessThan~1666
--operation mode is normal

D1L25 = D1_vector_x[8] # D1_vector_x[7];


--D1_vector_x[4] is vgaCalc:u2|VgaInterface:u1|vector_x[4]
--operation mode is normal

D1_vector_x[4]_lut_out = D1L6;
D1_vector_x[4] = DFFEAS(D1_vector_x[4]_lut_out, D1_clk, !reset, , , , , , );


--D1_vector_x[6] is vgaCalc:u2|VgaInterface:u1|vector_x[6]
--operation mode is normal

D1_vector_x[6]_lut_out = D1L8;
D1_vector_x[6] = DFFEAS(D1_vector_x[6]_lut_out, D1_clk, !reset, , , , , , );


--D1_vector_x[5] is vgaCalc:u2|VgaInterface:u1|vector_x[5]
--operation mode is normal

D1_vector_x[5]_lut_out = D1L01 & !D1L96;
D1_vector_x[5] = DFFEAS(D1_vector_x[5]_lut_out, D1_clk, !reset, , , , , , );


--D1L46 is vgaCalc:u2|VgaInterface:u1|process6~29
--operation mode is normal

D1L46 = D1_vector_x[4] & D1_vector_x[6] & D1_vector_x[5] # !D1_vector_x[4] & !D1_vector_x[6] & !D1_vector_x[5] # !D1_vector_x[9];


--D1_vector_y[4] is vgaCalc:u2|VgaInterface:u1|vector_y[4]
--operation mode is arithmetic

D1_vector_y[4]_carry_eqn = D1L98;
D1_vector_y[4]_lut_out = D1_vector_y[4] $ (!D1_vector_y[4]_carry_eqn);
D1_vector_y[4] = DFFEAS(D1_vector_y[4]_lut_out, D1_clk, !reset, , D1L96, , , , );

--D1L19 is vgaCalc:u2|VgaInterface:u1|vector_y[4]~237
--operation mode is arithmetic

D1L19 = CARRY(D1_vector_y[4] & (!D1L98));


--D1_vector_y[2] is vgaCalc:u2|VgaInterface:u1|vector_y[2]
--operation mode is arithmetic

D1_vector_y[2]_carry_eqn = D1L58;
D1_vector_y[2]_lut_out = D1_vector_y[2] $ (!D1_vector_y[2]_carry_eqn);
D1_vector_y[2] = DFFEAS(D1_vector_y[2]_lut_out, D1_clk, !reset, , D1L96, , , , );

--D1L78 is vgaCalc:u2|VgaInterface:u1|vector_y[2]~241
--operation mode is arithmetic

D1L78 = CARRY(D1_vector_y[2] & (!D1L58));


--D1_vector_y[1] is vgaCalc:u2|VgaInterface:u1|vector_y[1]
--operation mode is arithmetic

D1_vector_y[1]_carry_eqn = D1L38;
D1_vector_y[1]_lut_out = D1_vector_y[1] $ (D1_vector_y[1]_carry_eqn);
D1_vector_y[1] = DFFEAS(D1_vector_y[1]_lut_out, D1_clk, !reset, , D1L96, , , , );

--D1L58 is vgaCalc:u2|VgaInterface:u1|vector_y[1]~245
--operation mode is arithmetic

D1L58 = CARRY(!D1L38 # !D1_vector_y[1]);


--D1L66 is vgaCalc:u2|VgaInterface:u1|process7~33
--operation mode is normal

D1L66 = D1_vector_y[2] # !D1_vector_y[1];


--D1_vector_y[3] is vgaCalc:u2|VgaInterface:u1|vector_y[3]
--operation mode is arithmetic

D1_vector_y[3]_carry_eqn = D1L78;
D1_vector_y[3]_lut_out = D1_vector_y[3] $ (D1_vector_y[3]_carry_eqn);
D1_vector_y[3] = DFFEAS(D1_vector_y[3]_lut_out, D1_clk, !reset, , D1L96, , , , );

--D1L98 is vgaCalc:u2|VgaInterface:u1|vector_y[3]~249
--operation mode is arithmetic

D1L98 = CARRY(!D1L78 # !D1_vector_y[3]);


--D1_char_address[0] is vgaCalc:u2|VgaInterface:u1|char_address[0]
--operation mode is normal

D1_char_address[0]_lut_out = D1_vector_x[0] & (D1L53 # !D1L73);
D1_char_address[0] = DFFEAS(D1_char_address[0]_lut_out, D1_clk, VCC, , , , , , );


--D1_char_address[1] is vgaCalc:u2|VgaInterface:u1|char_address[1]
--operation mode is normal

D1_char_address[1]_lut_out = D1_vector_x[1] & (D1L53 # !D1L73);
D1_char_address[1] = DFFEAS(D1_char_address[1]_lut_out, D1_clk, VCC, , , , , , );


--D1_char_address[2] is vgaCalc:u2|VgaInterface:u1|char_address[2]
--operation mode is normal

D1_char_address[2]_lut_out = D1_vector_x[2] & (D1L53 # !D1L73);
D1_char_address[2] = DFFEAS(D1_char_address[2]_lut_out, D1_clk, VCC, , , , , , );


--D1_char_address[3] is vgaCalc:u2|VgaInterface:u1|char_address[3]
--operation mode is normal

D1_char_address[3]_lut_out = D1_vector_x[3] & (D1L53 # !D1L73);
D1_char_address[3] = DFFEAS(D1_char_address[3]_lut_out, D1_clk, VCC, , , , , , );


--D1_char_address[4] is vgaCalc:u2|VgaInterface:u1|char_address[4]
--operation mode is normal

D1_char_address[4]_lut_out = D1_vector_x[4] & (D1L53 # !D1L73);
D1_char_address[4] = DFFEAS(D1_char_address[4]_lut_out, D1_clk, VCC, , , , , , );


--D1_char_address[5] is vgaCalc:u2|VgaInterface:u1|char_address[5]
--operation mode is normal

D1_char_address[5]_lut_out = D1_vector_y[0] & (D1L53 # !D1L73);
D1_char_address[5] = DFFEAS(D1_char_address[5]_lut_out, D1_clk, VCC, , , , , , );


--D1_char_address[6] is vgaCalc:u2|VgaInterface:u1|char_address[6]
--operation mode is normal

D1_char_address[6]_lut_out = D1_vector_y[1] & (D1L53 # !D1L73);
D1_char_address[6] = DFFEAS(D1_char_address[6]_lut_out, D1_clk, VCC, , , , , , );


--D1_char_address[7] is vgaCalc:u2|VgaInterface:u1|char_address[7]
--operation mode is normal

D1_char_address[7]_lut_out = D1_vector_y[2] & (D1L53 # !D1L73);
D1_char_address[7] = DFFEAS(D1_char_address[7]_lut_out, D1_clk, VCC, , , , , , );


--D1_char_address[8] is vgaCalc:u2|VgaInterface:u1|char_address[8]
--operation mode is normal

D1_char_address[8]_lut_out = D1_vector_y[3] & (D1L53 # !D1L73);
D1_char_address[8] = DFFEAS(D1_char_address[8]_lut_out, D1_clk, VCC, , , , , , );


--D1_char_address[9] is vgaCalc:u2|VgaInterface:u1|char_address[9]
--operation mode is normal

D1_char_address[9]_lut_out = D1_vector_y[4] & (D1L53 # !D1L73);
D1_char_address[9] = DFFEAS(D1_char_address[9]_lut_out, D1_clk, VCC, , , , , , );


--D1_char_address[10] is vgaCalc:u2|VgaInterface:u1|char_address[10]
--operation mode is normal

D1_char_address[10]_lut_out = D1L26 & (D1_vga_data[16]) # !D1L26 & D1L14;
D1_char_address[10] = DFFEAS(D1_char_address[10]_lut_out, D1_clk, VCC, , , D1_vga_data[20], , D1L93, D1L36);


--D1_char_address[11] is vgaCalc:u2|VgaInterface:u1|char_address[11]
--operation mode is normal

D1_char_address[11]_lut_out = D1L26 & (D1_vga_data[4]) # !D1L26 & D1L34;
D1_char_address[11] = DFFEAS(D1_char_address[11]_lut_out, D1_clk, VCC, , , D1_vga_data[21], , D1L93, D1L36);


--H1_address_reg_a[0] is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|address_reg_a[0]
--operation mode is normal

H1_address_reg_a[0]_lut_out = D1_char_address[12];
H1_address_reg_a[0] = DFFEAS(H1_address_reg_a[0]_lut_out, D1_clk, VCC, , , , , , );


--H1_address_reg_a[1] is vgaCalc:u2|VgaInterface:u1|rom1:u1|altsyncram:altsyncram_component|altsyncram_n6q:auto_generated|address_reg_a[1]
--operation mode is normal

H1_address_reg_a[1]_lut_out = D1_char_address[13];
H1_address_reg_a[1] = DFFEAS(H1_address_reg_a[1]_lut_out, D1_clk, VCC, , , , , , );


--D1_char_address[13] is vgaCalc:u2|VgaInterface:u1|char_address[13]
--operation mode is normal

D1_char_address[13]_lut_out = D1L26 & (D1_vga_data[4]) # !D1L26 & D1L54;
D1_char_address[13] = DFFEAS(D1_char_address[13]_lut_out, D1_clk, VCC, , , D1_vga_data[23], , D1L93, D1L36);


--D1_char_address[12] is vgaCalc:u2|VgaInterface:u1|char_address[12]
--operation mode is normal

D1_char_address[12]_lut_out = D1L26 & (D1_vga_data[18]) # !D1L26 & D1L74;
D1_char_address[12] = DFFEAS(D1_char_address[12]_lut_out, D1_clk, VCC, , , D1_vga_data[22], , D1L93, D1L36);


--D1L76 is vgaCalc:u2|VgaInterface:u1|reduce_nor~73
--operation mode is normal

D1L76 = D1_vector_x[6] # D1_vector_x[5] # !D1_vector_x[8] # !D1_vector_x[9];


--D1_vector_x[3] is vgaCalc:u2|VgaInterface:u1|vector_x[3]
--operation mode is normal

D1_vector_x[3]_lut_out = D1L21;
D1_vector_x[3] = DFFEAS(D1_vector_x[3]_lut_out, D1_clk, !reset, , , , , , );


--D1_vector_x[2] is vgaCalc:u2|VgaInterface:u1|vector_x[2]
--operation mode is normal

D1_vector_x[2]_lut_out = D1L41;
D1_vector_x[2] = DFFEAS(D1_vector_x[2]_lut_out, D1_clk, !reset, , , , , , );


--D1L86 is vgaCalc:u2|VgaInterface:u1|reduce_nor~74
--operation mode is normal