vgaps2.tan.rpt

用VHDL写的一个小游戏

; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk50m          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk50m'                                                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------+---------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                   ; To                                          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------+---------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 36.06 MHz ( period = 27.734 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|va[0]                    ; clk50m     ; clk50m   ; None                        ; None                      ; 4.305 ns                ;
; N/A                                     ; 36.06 MHz ( period = 27.734 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|va[1]                    ; clk50m     ; clk50m   ; None                        ; None                      ; 4.305 ns                ;
; N/A                                     ; 36.06 MHz ( period = 27.734 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|va[3]                    ; clk50m     ; clk50m   ; None                        ; None                      ; 4.305 ns                ;
; N/A                                     ; 36.06 MHz ( period = 27.734 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|va[2]                    ; clk50m     ; clk50m   ; None                        ; None                      ; 4.305 ns                ;
; N/A                                     ; 36.63 MHz ( period = 27.300 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|opout[0]                 ; clk50m     ; clk50m   ; None                        ; None                      ; 4.088 ns                ;
; N/A                                     ; 36.63 MHz ( period = 27.300 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|opout[2]                 ; clk50m     ; clk50m   ; None                        ; None                      ; 4.088 ns                ;
; N/A                                     ; 36.85 MHz ( period = 27.134 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|STX.st2                  ; clk50m     ; clk50m   ; None                        ; None                      ; 4.005 ns                ;
; N/A                                     ; 37.06 MHz ( period = 26.982 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|STX.st4                  ; clk50m     ; clk50m   ; None                        ; None                      ; 3.929 ns                ;
; N/A                                     ; 37.39 MHz ( period = 26.742 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|vb[0]                    ; clk50m     ; clk50m   ; None                        ; None                      ; 3.809 ns                ;
; N/A                                     ; 37.39 MHz ( period = 26.742 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|vb[1]                    ; clk50m     ; clk50m   ; None                        ; None                      ; 3.809 ns                ;
; N/A                                     ; 37.39 MHz ( period = 26.742 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|vb[3]                    ; clk50m     ; clk50m   ; None                        ; None                      ; 3.809 ns                ;
; N/A                                     ; 37.39 MHz ( period = 26.742 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|vb[2]                    ; clk50m     ; clk50m   ; None                        ; None                      ; 3.809 ns                ;
; N/A                                     ; 38.56 MHz ( period = 25.936 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|op                       ; clk50m     ; clk50m   ; None                        ; None                      ; 3.406 ns                ;
; N/A                                     ; 38.57 MHz ( period = 25.928 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|STX.st1                  ; clk50m     ; clk50m   ; None                        ; None                      ; 3.402 ns                ;
; N/A                                     ; 38.89 MHz ( period = 25.716 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|STX.st0                  ; clk50m     ; clk50m   ; None                        ; None                      ; 3.296 ns                ;
; N/A                                     ; 38.90 MHz ( period = 25.706 ns )                    ; Readkey:u1|tempenable                  ; vgaCalc:u2|Calc:u2|STX.st3                  ; clk50m     ; clk50m   ; None                        ; None                      ; 3.291 ns                ;
; N/A                                     ; 49.33 MHz ( period = 20.271 ns )                    ; calcdata[2]                            ; vgaCalc:u2|Calc:u2|va[0]                    ; clk50m     ; clk50m   ; None                        ; None                      ; 5.727 ns                ;
; N/A                                     ; 49.33 MHz ( period = 20.271 ns )                    ; calcdata[2]                            ; vgaCalc:u2|Calc:u2|va[1]                    ; clk50m     ; clk50m   ; None                        ; None                      ; 5.727 ns                ;
; N/A                                     ; 49.33 MHz ( period = 20.271 ns )                    ; calcdata[2]                            ; vgaCalc:u2|Calc:u2|va[3]                    ; clk50m     ; clk50m   ; None                        ; None                      ; 5.727 ns                ;
; N/A                                     ; 49.33 MHz ( period = 20.271 ns )                    ; calcdata[2]                            ; vgaCalc:u2|Calc:u2|va[2]                    ; clk50m     ; clk50m   ; None                        ; None                      ; 5.727 ns                ;
; N/A                                     ; 49.83 MHz ( period = 20.070 ns )                    ; calcdata[3]                            ; vgaCalc:u2|Calc:u2|va[0]                    ; clk50m     ; clk50m   ; None                        ; None                      ; 5.526 ns                ;