dotprod1.v

用VERILOG语言编写的神经元权值连接的源代码,供大家享用,但是注释很少.

//  -------------------------------------------------------------
// 
//  Module: dotprod1
//  Simulink Path: ANN/Neural Network/Layer 1/IW{1,1}/dotprod1
//  Created: 2008-04-26 20:07:17
//  Hierarchy Level: 3
// 
// 
//  -------------------------------------------------------------

`timescale 1 ns / 1 ns

module dotprod1
          (
           clk,
           reset,
           enb,
           w_0,
           w_1,
           w_2,
           w_3,
           w_4,
           w_5,
           w_6,
           w_7,
           p_0,
           p_1,
           p_2,
           p_3,
           p_4,
           p_5,
           p_6,
           p_7,
           z
          );


  input   clk;
  input   reset;
  input   enb;
  input   [63:0] w_0;  // ufix64
  input   [63:0] w_1;  // ufix64
  input   [63:0] w_2;  // ufix64
  input   [63:0] w_3;  // ufix64
  input   [63:0] w_4;  // ufix64
  input   [63:0] w_5;  // ufix64
  input   [63:0] w_6;  // ufix64
  input   [63:0] w_7;  // ufix64
  input   [63:0] p_0;  // ufix64
  input   [63:0] p_1;  // ufix64
  input   [63:0] p_2;  // ufix64
  input   [63:0] p_3;  // ufix64
  input   [63:0] p_4;  // ufix64
  input   [63:0] p_5;  // ufix64
  input   [63:0] p_6;  // ufix64
  input   [63:0] p_7;  // ufix64
  output  [63:0] z;  // ufix64


  real w_0_1;  // double
  real w_1_1;  // double
  real w_2_1;  // double
  real w_3_1;  // double
  real w_4_1;  // double
  real w_5_1;  // double
  real w_6_1;  // double
  real w_7_1;  // double
  real w [0:7];  // double [8]
  real in_1_0;  // double
  wire [63:0] s;  // ufix64
  real in_1_1;  // double
  wire [63:0] s_1;  // ufix64
  real in_1_2;  // double
  wire [63:0] s_2;  // ufix64
  real in_1_3;  // double
  wire [63:0] s_3;  // ufix64
  real in_1_4;  // double
  wire [63:0] s_4;  // ufix64
  real in_1_5;  // double
  wire [63:0] s_5;  // ufix64
  real in_1_6;  // double
  wire [63:0] s_6;  // ufix64
  real in_1_7;  // double
  wire [63:0] s_7;  // ufix64
  real p_0_1;  // double
  real p_1_1;  // double
  real p_2_1;  // double
  real p_3_1;  // double
  real p_4_1;  // double
  real p_5_1;  // double
  real p_6_1;  // double
  real p_7_1;  // double
  real p [0:7];  // double [8]
  real in_2_0;  // double
  wire [63:0] s_8;  // ufix64
  real in_2_1;  // double
  wire [63:0] s_9;  // ufix64
  real in_2_2;  // double
  wire [63:0] s_10;  // ufix64
  real in_2_3;  // double
  wire [63:0] s_11;  // ufix64
  real in_2_4;  // double
  wire [63:0] s_12;  // ufix64
  real in_2_5;  // double
  wire [63:0] s_13;  // ufix64
  real in_2_6;  // double
  wire [63:0] s_14;  // ufix64
  real in_2_7;  // double
  wire [63:0] s_15;  // ufix64

  always @* w_0_1 <= $bitstoreal(w_0);
  always @* w_1_1 <= $bitstoreal(w_1);
  always @* w_2_1 <= $bitstoreal(w_2);
  always @* w_3_1 <= $bitstoreal(w_3);
  always @* w_4_1 <= $bitstoreal(w_4);
  always @* w_5_1 <= $bitstoreal(w_5);
  always @* w_6_1 <= $bitstoreal(w_6);
  always @* w_7_1 <= $bitstoreal(w_7);
  always @* w[0] <= w_0_1;
  always @* w[1] <= w_1_1;
  always @* w[2] <= w_2_1;
  always @* w[3] <= w_3_1;
  always @* w[4] <= w_4_1;
  always @* w[5] <= w_5_1;
  always @* w[6] <= w_6_1;
  always @* w[7] <= w_7_1;
  always @* in_1_0 <= w[0];
  assign s = $realtobits(in_1_0);
  always @* in_1_1 <= w[1];
  assign s_1 = $realtobits(in_1_1);
  always @* in_1_2 <= w[2];
  assign s_2 = $realtobits(in_1_2);
  always @* in_1_3 <= w[3];
  assign s_3 = $realtobits(in_1_3);
  always @* in_1_4 <= w[4];
  assign s_4 = $realtobits(in_1_4);
  always @* in_1_5 <= w[5];
  assign s_5 = $realtobits(in_1_5);
  always @* in_1_6 <= w[6];
  assign s_6 = $realtobits(in_1_6);
  always @* in_1_7 <= w[7];
  assign s_7 = $realtobits(in_1_7);
  always @* p_0_1 <= $bitstoreal(p_0);
  always @* p_1_1 <= $bitstoreal(p_1);
  always @* p_2_1 <= $bitstoreal(p_2);
  always @* p_3_1 <= $bitstoreal(p_3);
  always @* p_4_1 <= $bitstoreal(p_4);
  always @* p_5_1 <= $bitstoreal(p_5);
  always @* p_6_1 <= $bitstoreal(p_6);
  always @* p_7_1 <= $bitstoreal(p_7);
  always @* p[0] <= p_0_1;
  always @* p[1] <= p_1_1;
  always @* p[2] <= p_2_1;
  always @* p[3] <= p_3_1;
  always @* p[4] <= p_4_1;
  always @* p[5] <= p_5_1;
  always @* p[6] <= p_6_1;
  always @* p[7] <= p_7_1;
  always @* in_2_0 <= p[0];
  assign s_8 = $realtobits(in_2_0);
  always @* in_2_1 <= p[1];
  assign s_9 = $realtobits(in_2_1);
  always @* in_2_2 <= p[2];
  assign s_10 = $realtobits(in_2_2);
  always @* in_2_3 <= p[3];
  assign s_11 = $realtobits(in_2_3);
  always @* in_2_4 <= p[4];
  assign s_12 = $realtobits(in_2_4);
  always @* in_2_5 <= p[5];
  assign s_13 = $realtobits(in_2_5);
  always @* in_2_6 <= p[6];
  assign s_14 = $realtobits(in_2_6);
  always @* in_2_7 <= p[7];
  assign s_15 = $realtobits(in_2_7);
  Dot_Product   u_Dot_Product   (.clk(clk),
                                 .reset(reset),
                                 .enb(enb),
                                 .in_1_0(s),  // ufix64
                                 .in_1_1(s_1),  // ufix64
                                 .in_1_2(s_2),  // ufix64
                                 .in_1_3(s_3),  // ufix64
                                 .in_1_4(s_4),  // ufix64
                                 .in_1_5(s_5),  // ufix64
                                 .in_1_6(s_6),  // ufix64
                                 .in_1_7(s_7),  // ufix64
                                 .in_2_0(s_8),  // ufix64
                                 .in_2_1(s_9),  // ufix64
                                 .in_2_2(s_10),  // ufix64
                                 .in_2_3(s_11),  // ufix64
                                 .in_2_4(s_12),  // ufix64
                                 .in_2_5(s_13),  // ufix64
                                 .in_2_6(s_14),  // ufix64
                                 .in_2_7(s_15),  // ufix64
                                 .out_1(z)  // ufix64
                                 );

endmodule  // dotprod1