lcd_success.tan.qmsg

基于DE2实验板

{ "Info" "ITDB_TSU_RESULT" "datacnt\[0\] Reset clk -0.373 ns register " "Info: tsu for register \"datacnt\[0\]\" (data pin = \"Reset\", clock pin = \"clk\") is -0.373 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.495 ns + Longest pin register " "Info: + Longest pin to register delay is 8.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns Reset 1 PIN PIN_G26 13 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 13; PIN Node = 'Reset'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Reset } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.121 ns) + CELL(0.438 ns) 7.421 ns datacnt\[1\]~153 2 COMB LCCOMB_X2_Y26_N8 4 " "Info: 2: + IC(6.121 ns) + CELL(0.438 ns) = 7.421 ns; Loc. = LCCOMB_X2_Y26_N8; Fanout = 4; COMB Node = 'datacnt\[1\]~153'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.559 ns" { Reset datacnt[1]~153 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.414 ns) + CELL(0.660 ns) 8.495 ns datacnt\[0\] 3 REG LCFF_X1_Y26_N15 13 " "Info: 3: + IC(0.414 ns) + CELL(0.660 ns) = 8.495 ns; Loc. = LCFF_X1_Y26_N15; Fanout = 13; REG Node = 'datacnt\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.074 ns" { datacnt[1]~153 datacnt[0] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.960 ns ( 23.07 % ) " "Info: Total cell delay = 1.960 ns ( 23.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.535 ns ( 76.93 % ) " "Info: Total interconnect delay = 6.535 ns ( 76.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.495 ns" { Reset datacnt[1]~153 datacnt[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.495 ns" { Reset Reset~combout datacnt[1]~153 datacnt[0] } { 0.000ns 0.000ns 6.121ns 0.414ns } { 0.000ns 0.862ns 0.438ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.832 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.832 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.787 ns) 2.925 ns b\[12\] 3 REG LCFF_X31_Y25_N15 4 " "Info: 3: + IC(1.021 ns) + CELL(0.787 ns) = 2.925 ns; Loc. = LCFF_X31_Y25_N15; Fanout = 4; REG Node = 'b\[12\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.808 ns" { clk~clkctrl b[12] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.330 ns) + CELL(0.271 ns) 3.526 ns LessThan0~294 4 COMB LCCOMB_X31_Y25_N18 1 " "Info: 4: + IC(0.330 ns) + CELL(0.271 ns) = 3.526 ns; Loc. = LCCOMB_X31_Y25_N18; Fanout = 1; COMB Node = 'LessThan0~294'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.601 ns" { b[12] LessThan0~294 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.344 ns) + CELL(0.000 ns) 4.870 ns LessThan0~294clkctrl 5 COMB CLKCTRL_G8 3 " "Info: 5: + IC(1.344 ns) + CELL(0.000 ns) = 4.870 ns; Loc. = CLKCTRL_G8; Fanout = 3; COMB Node = 'LessThan0~294clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.344 ns" { LessThan0~294 LessThan0~294clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.787 ns) 6.671 ns s\[2\] 6 REG LCFF_X1_Y18_N21 3 " "Info: 6: + IC(1.014 ns) + CELL(0.787 ns) = 6.671 ns; Loc. = LCFF_X1_Y18_N21; Fanout = 3; REG Node = 's\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.801 ns" { LessThan0~294clkctrl s[2] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.633 ns) + CELL(0.000 ns) 7.304 ns s\[2\]~clkctrl 7 COMB CLKCTRL_G3 16 " "Info: 7: + IC(0.633 ns) + CELL(0.000 ns) = 7.304 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 's\[2\]~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.633 ns" { s[2] s[2]~clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.991 ns) + CELL(0.537 ns) 8.832 ns datacnt\[0\] 8 REG LCFF_X1_Y26_N15 13 " "Info: 8: + IC(0.991 ns) + CELL(0.537 ns) = 8.832 ns; Loc. = LCFF_X1_Y26_N15; Fanout = 13; REG Node = 'datacnt\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.528 ns" { s[2]~clkctrl datacnt[0] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.381 ns ( 38.28 % ) " "Info: Total cell delay = 3.381 ns ( 38.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.451 ns ( 61.72 % ) " "Info: Total interconnect delay = 5.451 ns ( 61.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.832 ns" { clk clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl datacnt[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.832 ns" { clk clk~combout clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl datacnt[0] } { 0.000ns 0.000ns 0.118ns 1.021ns 0.330ns 1.344ns 1.014ns 0.633ns 0.991ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.271ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.495 ns" { Reset datacnt[1]~153 datacnt[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.495 ns" { Reset Reset~combout datacnt[1]~153 datacnt[0] } { 0.000ns 0.000ns 6.121ns 0.414ns } { 0.000ns 0.862ns 0.438ns 0.660ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.832 ns" { clk clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl datacnt[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.832 ns" { clk clk~combout clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl datacnt[0] } { 0.000ns 0.000ns 0.118ns 1.021ns 0.330ns 1.344ns 1.014ns 0.633ns 0.991ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.271ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk rs rs~reg0 14.160 ns register " "Info: tco from clock \"clk\" to destination pin \"rs\" through register \"rs~reg0\" is 14.160 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.263 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 10.263 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.787 ns) 2.925 ns b\[3\] 3 REG LCFF_X30_Y25_N11 4 " "Info: 3: + IC(1.021 ns) + CELL(0.787 ns) = 2.925 ns; Loc. = LCFF_X30_Y25_N11; Fanout = 4; REG Node = 'b\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.808 ns" { clk~clkctrl b[3] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.520 ns) + CELL(0.438 ns) 3.883 ns LessThan0~292 4 COMB LCCOMB_X31_Y25_N0 1 " "Info: 4: + IC(0.520 ns) + CELL(0.438 ns) = 3.883 ns; Loc. = LCCOMB_X31_Y25_N0; Fanout = 1; COMB Node = 'LessThan0~292'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.958 ns" { b[3] LessThan0~292 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.415 ns) 4.553 ns LessThan0~293 5 COMB LCCOMB_X31_Y25_N2 1 " "Info: 5: + IC(0.255 ns) + CELL(0.415 ns) = 4.553 ns; Loc. = LCCOMB_X31_Y25_N2; Fanout = 1; COMB Node = 'LessThan0~293'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.670 ns" { LessThan0~292 LessThan0~293 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.251 ns) + CELL(0.149 ns) 4.953 ns LessThan0~294 6 COMB LCCOMB_X31_Y25_N18 1 " "Info: 6: + IC(0.251 ns) + CELL(0.149 ns) = 4.953 ns; Loc. = LCCOMB_X31_Y25_N18; Fanout = 1; COMB Node = 'LessThan0~294'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { LessThan0~293 LessThan0~294 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.344 ns) + CELL(0.000 ns) 6.297 ns LessThan0~294clkctrl 7 COMB CLKCTRL_G8 3 " "Info: 7: + IC(1.344 ns) + CELL(0.000 ns) = 6.297 ns; Loc. = CLKCTRL_G8; Fanout = 3; COMB Node = 'LessThan0~294clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.344 ns" { LessThan0~294 LessThan0~294clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.787 ns) 8.098 ns s\[2\] 8 REG LCFF_X1_Y18_N21 3 " "Info: 8: + IC(1.014 ns) + CELL(0.787 ns) = 8.098 ns; Loc. = LCFF_X1_Y18_N21; Fanout = 3; REG Node = 's\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.801 ns" { LessThan0~294clkctrl s[2] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.633 ns) + CELL(0.000 ns) 8.731 ns s\[2\]~clkctrl 9 COMB CLKCTRL_G3 16 " "Info: 9: + IC(0.633 ns) + CELL(0.000 ns) = 8.731 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 's\[2\]~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.633 ns" { s[2] s[2]~clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.537 ns) 10.263 ns rs~reg0 10 REG LCFF_X2_Y26_N31 1 " "Info: 10: + IC(0.995 ns) + CELL(0.537 ns) = 10.263 ns; Loc. = LCFF_X2_Y26_N31; Fanout = 1; REG Node = 'rs~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.532 ns" { s[2]~clkctrl rs~reg0 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.112 ns ( 40.07 % ) " "Info: Total cell delay = 4.112 ns ( 40.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.151 ns ( 59.93 % ) " "Info: Total interconnect delay = 6.151 ns ( 59.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.263 ns" { clk clk~clkctrl b[3] LessThan0~292 LessThan0~293 LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl rs~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.263 ns" { clk clk~combout clk~clkctrl b[3] LessThan0~292 LessThan0~293 LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl rs~reg0 } { 0.000ns 0.000ns 0.118ns 1.021ns 0.520ns 0.255ns 0.251ns 1.344ns 1.014ns 0.633ns 0.995ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.438ns 0.415ns 0.149ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.647 ns + Longest register pin " "Info: + Longest register to pin delay is 3.647 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rs~reg0 1 REG LCFF_X2_Y26_N31 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y26_N31; Fanout = 1; REG Node = 'rs~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rs~reg0 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(2.642 ns) 3.647 ns rs 2 PIN PIN_K1 0 " "Info: 2: + IC(1.005 ns) + CELL(2.642 ns) = 3.647 ns; Loc. = PIN_K1; Fanout = 0; PIN Node = 'rs'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.647 ns" { rs~reg0 rs } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.642 ns ( 72.44 % ) " "Info: Total cell delay = 2.642 ns ( 72.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.005 ns ( 27.56 % ) " "Info: Total interconnect delay = 1.005 ns ( 27.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.647 ns" {