lcd_success.tan.qmsg

基于DE2实验板

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 66 " "Warning: Circuit may not operate. Detected 66 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "s\[2\] s\[2\] clk 1.036 ns " "Info: Found hold time violation between source  pin or register \"s\[2\]\" and destination pin or register \"s\[2\]\" for clock \"clk\" (Hold time is 1.036 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.427 ns + Largest " "Info: + Largest clock skew is 1.427 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.848 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.787 ns) 2.925 ns b\[3\] 3 REG LCFF_X30_Y25_N11 4 " "Info: 3: + IC(1.021 ns) + CELL(0.787 ns) = 2.925 ns; Loc. = LCFF_X30_Y25_N11; Fanout = 4; REG Node = 'b\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.808 ns" { clk~clkctrl b[3] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.520 ns) + CELL(0.438 ns) 3.883 ns LessThan0~292 4 COMB LCCOMB_X31_Y25_N0 1 " "Info: 4: + IC(0.520 ns) + CELL(0.438 ns) = 3.883 ns; Loc. = LCCOMB_X31_Y25_N0; Fanout = 1; COMB Node = 'LessThan0~292'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.958 ns" { b[3] LessThan0~292 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.415 ns) 4.553 ns LessThan0~293 5 COMB LCCOMB_X31_Y25_N2 1 " "Info: 5: + IC(0.255 ns) + CELL(0.415 ns) = 4.553 ns; Loc. = LCCOMB_X31_Y25_N2; Fanout = 1; COMB Node = 'LessThan0~293'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.670 ns" { LessThan0~292 LessThan0~293 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.251 ns) + CELL(0.149 ns) 4.953 ns LessThan0~294 6 COMB LCCOMB_X31_Y25_N18 1 " "Info: 6: + IC(0.251 ns) + CELL(0.149 ns) = 4.953 ns; Loc. = LCCOMB_X31_Y25_N18; Fanout = 1; COMB Node = 'LessThan0~294'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { LessThan0~293 LessThan0~294 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.344 ns) + CELL(0.000 ns) 6.297 ns LessThan0~294clkctrl 7 COMB CLKCTRL_G8 3 " "Info: 7: + IC(1.344 ns) + CELL(0.000 ns) = 6.297 ns; Loc. = CLKCTRL_G8; Fanout = 3; COMB Node = 'LessThan0~294clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.344 ns" { LessThan0~294 LessThan0~294clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.537 ns) 7.848 ns s\[2\] 8 REG LCFF_X1_Y18_N21 3 " "Info: 8: + IC(1.014 ns) + CELL(0.537 ns) = 7.848 ns; Loc. = LCFF_X1_Y18_N21; Fanout = 3; REG Node = 's\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.551 ns" { LessThan0~294clkctrl s[2] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.325 ns ( 42.37 % ) " "Info: Total cell delay = 3.325 ns ( 42.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.523 ns ( 57.63 % ) " "Info: Total interconnect delay = 4.523 ns ( 57.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.848 ns" { clk clk~clkctrl b[3] LessThan0~292 LessThan0~293 LessThan0~294 LessThan0~294clkctrl s[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.848 ns" { clk clk~combout clk~clkctrl b[3] LessThan0~292 LessThan0~293 LessThan0~294 LessThan0~294clkctrl s[2] } { 0.000ns 0.000ns 0.118ns 1.021ns 0.520ns 0.255ns 0.251ns 1.344ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.438ns 0.415ns 0.149ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.421 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 6.421 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.787 ns) 2.925 ns b\[12\] 3 REG LCFF_X31_Y25_N15 4 " "Info: 3: + IC(1.021 ns) + CELL(0.787 ns) = 2.925 ns; Loc. = LCFF_X31_Y25_N15; Fanout = 4; REG Node = 'b\[12\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.808 ns" { clk~clkctrl b[12] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.330 ns) + CELL(0.271 ns) 3.526 ns LessThan0~294 4 COMB LCCOMB_X31_Y25_N18 1 " "Info: 4: + IC(0.330 ns) + CELL(0.271 ns) = 3.526 ns; Loc. = LCCOMB_X31_Y25_N18; Fanout = 1; COMB Node = 'LessThan0~294'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.601 ns" { b[12] LessThan0~294 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.344 ns) + CELL(0.000 ns) 4.870 ns LessThan0~294clkctrl 5 COMB CLKCTRL_G8 3 " "Info: 5: + IC(1.344 ns) + CELL(0.000 ns) = 4.870 ns; Loc. = CLKCTRL_G8; Fanout = 3; COMB Node = 'LessThan0~294clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.344 ns" { LessThan0~294 LessThan0~294clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.537 ns) 6.421 ns s\[2\] 6 REG LCFF_X1_Y18_N21 3 " "Info: 6: + IC(1.014 ns) + CELL(0.537 ns) = 6.421 ns; Loc. = LCFF_X1_Y18_N21; Fanout = 3; REG Node = 's\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.551 ns" { LessThan0~294clkctrl s[2] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.594 ns ( 40.40 % ) " "Info: Total cell delay = 2.594 ns ( 40.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.827 ns ( 59.60 % ) " "Info: Total interconnect delay = 3.827 ns ( 59.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.421 ns" { clk clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.421 ns" { clk clk~combout clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] } { 0.000ns 0.000ns 0.118ns 1.021ns 0.330ns 1.344ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.271ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.848 ns" { clk clk~clkctrl b[3] LessThan0~292 LessThan0~293 LessThan0~294 LessThan0~294clkctrl s[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.848 ns" { clk clk~combout clk~clkctrl b[3] LessThan0~292 LessThan0~293 LessThan0~294 LessThan0~294clkctrl s[2] } { 0.000ns 0.000ns 0.118ns 1.021ns 0.520ns 0.255ns 0.251ns 1.344ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.438ns 0.415ns 0.149ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.421 ns" { clk clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.421 ns" { clk clk~combout clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] } { 0.000ns 0.000ns 0.118ns 1.021ns 0.330ns 1.344ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.271ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns - Shortest register register " "Info: - Shortest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns s\[2\] 1 REG LCFF_X1_Y18_N21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y18_N21; Fanout = 3; REG Node = 's\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { s[2] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns s\[2\]~34 2 COMB LCCOMB_X1_Y18_N20 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X1_Y18_N20; Fanout = 1; COMB Node = 's\[2\]~34'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.323 ns" { s[2] s[2]~34 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns s\[2\] 3 REG LCFF_X1_Y18_N21 3 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X1_Y18_N21; Fanout = 3; REG Node = 's\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { s[2]~34 s[2] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.407 ns" { s[2] s[2]~34 s[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.407 ns" { s[2] s[2]~34 s[2] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.848 ns" { clk clk~clkctrl b[3] LessThan0~292 LessThan0~293 LessThan0~294 LessThan0~294clkctrl s[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.848 ns" { clk clk~combout clk~clkctrl b[3] LessThan0~292 LessThan0~293 LessThan0~294 LessThan0~294clkctrl s[2] } { 0.000ns 0.000ns 0.118ns 1.021ns 0.520ns 0.255ns 0.251ns 1.344ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.438ns 0.415ns 0.149ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.421 ns" { clk clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.421 ns" { clk clk~combout clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] } { 0.000ns 0.000ns 0.118ns 1.021ns 0.330ns 1.344ns 1.014ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.271ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.407 ns" { s[2] s[2]~34 s[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.407 ns" { s[2] s[2]~34 s[2] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}