lcd_success.tan.qmsg

基于DE2实验板

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "20 " "Warning: Found 20 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "b\[2\] " "Info: Detected ripple clock \"b\[2\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "b\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "b\[1\] " "Info: Detected ripple clock \"b\[1\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "b\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "b\[0\] " "Info: Detected ripple clock \"b\[0\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "b\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "b\[10\] " "Info: Detected ripple clock \"b\[10\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "b\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "b\[9\] " "Info: Detected ripple clock \"b\[9\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "b\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "b\[8\] " "Info: Detected ripple clock \"b\[8\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "b\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "b\[5\] " "Info: Detected ripple clock \"b\[5\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "b\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "b\[4\] " "Info: Detected ripple clock \"b\[4\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "b\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "b\[6\] " "Info: Detected ripple clock \"b\[6\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "b\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "b\[3\] " "Info: Detected ripple clock \"b\[3\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "b\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "LessThan0~291 " "Info: Detected gated clock \"LessThan0~291\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LessThan0~291" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "LessThan0~290 " "Info: Detected gated clock \"LessThan0~290\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LessThan0~290" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "LessThan0~292 " "Info: Detected gated clock \"LessThan0~292\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LessThan0~292" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "b\[7\] " "Info: Detected ripple clock \"b\[7\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "b\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "LessThan0~293 " "Info: Detected gated clock \"LessThan0~293\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LessThan0~293" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "b\[12\] " "Info: Detected ripple clock \"b\[12\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "b\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "b\[11\] " "Info: Detected ripple clock \"b\[11\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "b\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "b\[13\] " "Info: Detected ripple clock \"b\[13\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "b\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "LessThan0~294 " "Info: Detected gated clock \"LessThan0~294\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LessThan0~294" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "s\[2\] " "Info: Detected ripple clock \"s\[2\]\" as buffer" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "s\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register datacnt\[0\] register state.s2 286.04 MHz 3.496 ns Internal " "Info: Clock \"clk\" has Internal fmax of 286.04 MHz between source register \"datacnt\[0\]\" and destination register \"state.s2\" (period= 3.496 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.859 ns + Longest register register " "Info: + Longest register to register delay is 1.859 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns datacnt\[0\] 1 REG LCFF_X1_Y26_N15 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y26_N15; Fanout = 13; REG Node = 'datacnt\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { datacnt[0] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.492 ns) + CELL(0.150 ns) 0.642 ns Selector0~106 2 COMB LCCOMB_X1_Y26_N28 6 " "Info: 2: + IC(0.492 ns) + CELL(0.150 ns) = 0.642 ns; Loc. = LCCOMB_X1_Y26_N28; Fanout = 6; COMB Node = 'Selector0~106'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.642 ns" { datacnt[0] Selector0~106 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.695 ns) + CELL(0.438 ns) 1.775 ns Selector12~88 3 COMB LCCOMB_X2_Y26_N0 1 " "Info: 3: + IC(0.695 ns) + CELL(0.438 ns) = 1.775 ns; Loc. = LCCOMB_X2_Y26_N0; Fanout = 1; COMB Node = 'Selector12~88'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.133 ns" { Selector0~106 Selector12~88 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.859 ns state.s2 4 REG LCFF_X2_Y26_N1 4 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 1.859 ns; Loc. = LCFF_X2_Y26_N1; Fanout = 4; REG Node = 'state.s2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Selector12~88 state.s2 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.672 ns ( 36.15 % ) " "Info: Total cell delay = 0.672 ns ( 36.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.187 ns ( 63.85 % ) " "Info: Total interconnect delay = 1.187 ns ( 63.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.859 ns" { datacnt[0] Selector0~106 Selector12~88 state.s2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.859 ns" { datacnt[0] Selector0~106 Selector12~88 state.s2 } { 0.000ns 0.492ns 0.695ns 0.000ns } { 0.000ns 0.150ns 0.438ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.423 ns - Smallest " "Info: - Smallest clock skew is -1.423 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.836 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.836 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.787 ns) 2.925 ns b\[12\] 3 REG LCFF_X31_Y25_N15 4 " "Info: 3: + IC(1.021 ns) + CELL(0.787 ns) = 2.925 ns; Loc. = LCFF_X31_Y25_N15; Fanout = 4; REG Node = 'b\[12\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.808 ns" { clk~clkctrl b[12] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.330 ns) + CELL(0.271 ns) 3.526 ns LessThan0~294 4 COMB LCCOMB_X31_Y25_N18 1 " "Info: 4: + IC(0.330 ns) + CELL(0.271 ns) = 3.526 ns; Loc. = LCCOMB_X31_Y25_N18; Fanout = 1; COMB Node = 'LessThan0~294'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.601 ns" { b[12] LessThan0~294 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.344 ns) + CELL(0.000 ns) 4.870 ns LessThan0~294clkctrl 5 COMB CLKCTRL_G8 3 " "Info: 5: + IC(1.344 ns) + CELL(0.000 ns) = 4.870 ns; Loc. = CLKCTRL_G8; Fanout = 3; COMB Node = 'LessThan0~294clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.344 ns" { LessThan0~294 LessThan0~294clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.787 ns) 6.671 ns s\[2\] 6 REG LCFF_X1_Y18_N21 3 " "Info: 6: + IC(1.014 ns) + CELL(0.787 ns) = 6.671 ns; Loc. = LCFF_X1_Y18_N21; Fanout = 3; REG Node = 's\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.801 ns" { LessThan0~294clkctrl s[2] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.633 ns) + CELL(0.000 ns) 7.304 ns s\[2\]~clkctrl 7 COMB CLKCTRL_G3 16 " "Info: 7: + IC(0.633 ns) + CELL(0.000 ns) = 7.304 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 's\[2\]~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.633 ns" { s[2] s[2]~clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.537 ns) 8.836 ns state.s2 8 REG LCFF_X2_Y26_N1 4 " "Info: 8: + IC(0.995 ns) + CELL(0.537 ns) = 8.836 ns; Loc. = LCFF_X2_Y26_N1; Fanout = 4; REG Node = 'state.s2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.532 ns" { s[2]~clkctrl state.s2 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.381 ns ( 38.26 % ) " "Info: Total cell delay = 3.381 ns ( 38.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.455 ns ( 61.74 % ) " "Info: Total interconnect delay = 5.455 ns ( 61.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.836 ns" { clk clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl state.s2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.836 ns" { clk clk~combout clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl state.s2 } { 0.000ns 0.000ns 0.118ns 1.021ns 0.330ns 1.344ns 1.014ns 0.633ns 0.995ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.271ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.259 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 10.259 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.787 ns) 2.925 ns b\[3\] 3 REG LCFF_X30_Y25_N11 4 " "Info: 3: + IC(1.021 ns) + CELL(0.787 ns) = 2.925 ns; Loc. = LCFF_X30_Y25_N11; Fanout = 4; REG Node = 'b\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.808 ns" { clk~clkctrl b[3] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.520 ns) + CELL(0.438 ns) 3.883 ns LessThan0~292 4 COMB LCCOMB_X31_Y25_N0 1 " "Info: 4: + IC(0.520 ns) + CELL(0.438 ns) = 3.883 ns; Loc. = LCCOMB_X31_Y25_N0; Fanout = 1; COMB Node = 'LessThan0~292'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.958 ns" { b[3] LessThan0~292 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.415 ns) 4.553 ns LessThan0~293 5 COMB LCCOMB_X31_Y25_N2 1 " "Info: 5: + IC(0.255 ns) + CELL(0.415 ns) = 4.553 ns; Loc. = LCCOMB_X31_Y25_N2; Fanout = 1; COMB Node = 'LessThan0~293'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.670 ns" { LessThan0~292 LessThan0~293 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.251 ns) + CELL(0.149 ns) 4.953 ns LessThan0~294 6 COMB LCCOMB_X31_Y25_N18 1 " "Info: 6: + IC(0.251 ns) + CELL(0.149 ns) = 4.953 ns; Loc. = LCCOMB_X31_Y25_N18; Fanout = 1; COMB Node = 'LessThan0~294'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { LessThan0~293 LessThan0~294 } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.344 ns) + CELL(0.000 ns) 6.297 ns LessThan0~294clkctrl 7 COMB CLKCTRL_G8 3 " "Info: 7: + IC(1.344 ns) + CELL(0.000 ns) = 6.297 ns; Loc. = CLKCTRL_G8; Fanout = 3; COMB Node = 'LessThan0~294clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.344 ns" { LessThan0~294 LessThan0~294clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.787 ns) 8.098 ns s\[2\] 8 REG LCFF_X1_Y18_N21 3 " "Info: 8: + IC(1.014 ns) + CELL(0.787 ns) = 8.098 ns; Loc. = LCFF_X1_Y18_N21; Fanout = 3; REG Node = 's\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.801 ns" { LessThan0~294clkctrl s[2] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.633 ns) + CELL(0.000 ns) 8.731 ns s\[2\]~clkctrl 9 COMB CLKCTRL_G3 16 " "Info: 9: + IC(0.633 ns) + CELL(0.000 ns) = 8.731 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 's\[2\]~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.633 ns" { s[2] s[2]~clkctrl } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.991 ns) + CELL(0.537 ns) 10.259 ns datacnt\[0\] 10 REG LCFF_X1_Y26_N15 13 " "Info: 10: + IC(0.991 ns) + CELL(0.537 ns) = 10.259 ns; Loc. = LCFF_X1_Y26_N15; Fanout = 13; REG Node = 'datacnt\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.528 ns" { s[2]~clkctrl datacnt[0] } "NODE_NAME" } } { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.112 ns ( 40.08 % ) " "Info: Total cell delay = 4.112 ns ( 40.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.147 ns ( 59.92 % ) " "Info: Total interconnect delay = 6.147 ns ( 59.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.259 ns" { clk clk~clkctrl b[3] LessThan0~292 LessThan0~293 LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl datacnt[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.259 ns" { clk clk~combout clk~clkctrl b[3] LessThan0~292 LessThan0~293 LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl datacnt[0] } { 0.000ns 0.000ns 0.118ns 1.021ns 0.520ns 0.255ns 0.251ns 1.344ns 1.014ns 0.633ns 0.991ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.438ns 0.415ns 0.149ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.836 ns" { clk clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl state.s2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.836 ns" { clk clk~combout clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl state.s2 } { 0.000ns 0.000ns 0.118ns 1.021ns 0.330ns 1.344ns 1.014ns 0.633ns 0.995ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.271ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.259 ns" { clk clk~clkctrl b[3] LessThan0~292 LessThan0~293 LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl datacnt[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.259 ns" { clk clk~combout clk~clkctrl b[3] LessThan0~292 LessThan0~293 LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl datacnt[0] } { 0.000ns 0.000ns 0.118ns 1.021ns 0.520ns 0.255ns 0.251ns 1.344ns 1.014ns 0.633ns 0.991ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.438ns 0.415ns 0.149ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.859 ns" { datacnt[0] Selector0~106 Selector12~88 state.s2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.859 ns" { datacnt[0] Selector0~106 Selector12~88 state.s2 } { 0.000ns 0.492ns 0.695ns 0.000ns } { 0.000ns 0.150ns 0.438ns 0.084ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.836 ns" { clk clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl state.s2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.836 ns" { clk clk~combout clk~clkctrl b[12] LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl state.s2 } { 0.000ns 0.000ns 0.118ns 1.021ns 0.330ns 1.344ns 1.014ns 0.633ns 0.995ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.271ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.259 ns" { clk clk~clkctrl b[3] LessThan0~292 LessThan0~293 LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl datacnt[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.259 ns" { clk clk~combout clk~clkctrl b[3] LessThan0~292 LessThan0~293 LessThan0~294 LessThan0~294clkctrl s[2] s[2]~clkctrl datacnt[0] } { 0.000ns 0.000ns 0.118ns 1.021ns 0.520ns 0.255ns 0.251ns 1.344ns 1.014ns 0.633ns 0.991ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.438ns 0.415ns 0.149ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}