jsq.vhd

来自「四人抢答器」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jsq is 
  port (clr, en,clk:in std_logic;
		sp:out std_logic;
        qa:out std_logic_vector (3 downto 0);
        qb:out std_logic_vector (3 downto 0));
end entity jsq;
architecture art of jsq is
begin 
process(clk,clr)is
  variable tmpa:std_logic_vector (3 downto 0);
  variable tmpb:std_logic_vector (3 downto 0);
  begin 
if tmpa="0000"and tmpb="0000"then
sp<='1';
else sp<='0';
end if;
  if clr='1'then tmpa:= "0010";tmpb:= "0000";
     elsif clk'event and clk='1'then
    	if  en='1'then
          if tmpb="0000" then tmpb:="1001";tmpa:=tmpa-1;
          else tmpb:=tmpb-1;
          end if ;
       end if;
      end if;
qa<=tmpa;qb<=tmpb;
end process;
end;