jsq.rpt

四人抢答器

Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                    e:\ccw\jsq.rpt
jsq

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                 Logic cells placed in LAB 'B'
        +----------------------- LC27 |LPM_ADD_SUB:81|addcore:adder|addcore:adder0|gcp2
        | +--------------------- LC28 |LPM_ADD_SUB:86|addcore:adder|addcore:adder0|gcp2
        | | +------------------- LC24 qa0
        | | | +----------------- LC23 qa1
        | | | | +--------------- LC22 qa2
        | | | | | +------------- LC21 qa3
        | | | | | | +----------- LC20 qb0
        | | | | | | | +--------- LC19 qb1
        | | | | | | | | +------- LC18 qb2
        | | | | | | | | | +----- LC17 qb3
        | | | | | | | | | | +--- LC26 sp
        | | | | | | | | | | | +- LC25 ~48~1
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC27 -> - - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:81|addcore:adder|addcore:adder0|gcp2
LC28 -> - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:86|addcore:adder|addcore:adder0|gcp2
LC24 -> - - * * * * - - - - * * | - * | <-- qa0
LC23 -> * - - * * - - - - - * * | - * | <-- qa1
LC22 -> * - - - * - - - - - * * | - * | <-- qa2
LC21 -> - - - - - * - - - - * * | - * | <-- qa3
LC20 -> - - * * * * * * * * * * | - * | <-- qb0
LC19 -> - * * * * * - * * * * * | - * | <-- qb1
LC18 -> - * * * * * - * * * * * | - * | <-- qb2
LC17 -> - - * * * * - * * * * * | - * | <-- qb3
LC25 -> - - - - - - - - - - * * | - * | <-- ~48~1

Pin
43   -> - - - - - - - - - - - - | - - | <-- clk
4    -> - - * * * * * * * * - - | - * | <-- clr
5    -> - - * * * * * * * * - - | - * | <-- en


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                    e:\ccw\jsq.rpt
jsq

** EQUATIONS **

clk      : INPUT;
clr      : INPUT;
en       : INPUT;

-- Node name is 'qa0' = 'tmpa0' 
-- Equation name is 'qa0', location is LC024, type is output.
 qa0     = TFFE( _EQ001, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ001 =  en & !qb0 & !qb1 & !qb2 & !qb3;

-- Node name is 'qa1' = 'tmpa1' 
-- Equation name is 'qa1', location is LC023, type is output.
 qa1     = TFFE( _EQ002, GLOBAL( clk),  VCC, !clr,  VCC);
  _EQ002 =  en & !qa0 & !qb0 & !qb1 & !qb2 & !qb3;

-- Node name is 'qa2' = 'tmpa2' 
-- Equation name is 'qa2', location is LC022, type is output.
 qa2     = TFFE( _EQ003, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ003 =  en & !qa0 & !qa1 & !qb0 & !qb1 & !qb2 & !qb3;

-- Node name is 'qa3' = 'tmpa3' 
-- Equation name is 'qa3', location is LC021, type is output.
 qa3     = TFFE( _EQ004, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ004 =  en & !_LC027 & !qa0 & !qb0 & !qb1 & !qb2 & !qb3;

-- Node name is 'qb0' = 'tmpb0' 
-- Equation name is 'qb0', location is LC020, type is output.
 qb0     = TFFE( en, GLOBAL( clk), !clr,  VCC,  VCC);

-- Node name is 'qb1' = 'tmpb1' 
-- Equation name is 'qb1', location is LC019, type is output.
 qb1     = TFFE( _EQ005, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ005 =  en & !qb0 & !qb1 &  qb3
         #  en & !qb0 & !qb1 &  qb2
         #  en & !qb0 &  qb1;

-- Node name is 'qb2' = 'tmpb2' 
-- Equation name is 'qb2', location is LC018, type is output.
 qb2     = TFFE( _EQ006, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ006 =  en & !qb0 & !qb1 & !qb2 &  qb3
         #  en & !qb0 & !qb1 &  qb2;

-- Node name is 'qb3' = 'tmpb3' 
-- Equation name is 'qb3', location is LC017, type is output.
 qb3     = TFFE( _EQ007, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ007 =  en & !qb0 & !qb1 & !qb2 & !qb3
         #  en & !_LC028 & !qb0;

-- Node name is 'sp' 
-- Equation name is 'sp', location is LC026, type is output.
 sp      = LCELL( _EQ008 $  _EQ009);
  _EQ008 =  _LC025 &  _X001;
  _X001  = EXP(!qa0 & !qa1 & !qa2 & !qa3 & !qb0 & !qb1 & !qb2 & !qb3);
  _EQ009 = !qa0 & !qa1 & !qa2 & !qa3 & !qb0 & !qb1 & !qb2 & !qb3;

-- Node name is '|LPM_ADD_SUB:81|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL( _EQ010 $  qa2);
  _EQ010 =  qa1 & !qa2;

-- Node name is '|LPM_ADD_SUB:86|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC028', type is buried 
_LC028   = LCELL( _EQ011 $  qb2);
  _EQ011 =  qb1 & !qb2;

-- Node name is '~48~1' 
-- Equation name is '~48~1', location is LC025, type is buried.
-- synthesized logic cell 
_LC025   = LCELL( _EQ012 $  _LC025);
  _EQ012 = !_LC025 & !qa0 & !qa1 & !qa2 & !qa3 & !qb0 & !qb1 & !qb2 & !qb3;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                             e:\ccw\jsq.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,287K