qdjb.rpt

四人抢答器

LC18 -> - - * - - - - - - - - - - - - - | - * | <-- C1
LC20 -> - - - * - - - - - - - - - - - - | - * | <-- D1
LC22 -> - - - - - - - - * - * - - - - - | - * | <-- ~376~1
LC21 -> - - - - - - - - - * - - - - - - | - * | <-- ~382~1
LC23 -> - - - - - - - * - - - - * - - - | - * | <-- ~397~1
LC24 -> - - - - - - - - - - - * - - - - | - * | <-- ~403~1

Pin
4    -> * * * * * * * * * * * * * * * * | * * | <-- A
7    -> * * * * * * * * * * * * * * * * | * * | <-- B
6    -> * * * * * * * * * * * * * * * * | * * | <-- C
8    -> * * * * * * * * * - * - * * * * | - * | <-- CLR
5    -> * * * * * * * * * * * * * * * * | * * | <-- D
LC4  -> - - - - - - * - - - - - - * - - | - * | <-- ~418~1
LC8  -> - - - - - * - - - - - - - - * - | - * | <-- ~439~1
LC12 -> - - - - * - - - - - - - - - - * | - * | <-- ~460~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                   d:\ccw\qdjb.rpt
qdjb

** EQUATIONS **

A        : INPUT;
B        : INPUT;
C        : INPUT;
CLR      : INPUT;
D        : INPUT;

-- Node name is 'A1' = '~298~1' 
-- Equation name is 'A1', location is LC019, type is output.
 A1      = LCELL( _EQ001 $  VCC);
  _EQ001 = !A & !B & !CLR &  _X001
         # !A & !C & !CLR & !D
         # !A1 &  _X002;
  _X001  = EXP( C &  D);
  _X002  = EXP(!B & !C & !CLR & !D);

-- Node name is 'B1' = '~319~1' 
-- Equation name is 'B1', location is LC017, type is output.
 B1      = LCELL( _EQ002 $  VCC);
  _EQ002 = !B & !C & !CLR &  _X003
         # !A & !B & !CLR & !D
         # !B1 &  _X004;
  _X003  = EXP( A &  D);
  _X004  = EXP(!A & !C & !CLR & !D);

-- Node name is 'C1' = '~340~1' 
-- Equation name is 'C1', location is LC018, type is output.
 C1      = LCELL( _EQ003 $  VCC);
  _EQ003 = !B & !C & !CLR &  _X003
         # !A & !C & !CLR & !D
         # !C1 &  _X005;
  _X003  = EXP( A &  D);
  _X005  = EXP(!A & !B & !CLR & !D);

-- Node name is 'D1' = '~361~1' 
-- Equation name is 'D1', location is LC020, type is output.
 D1      = LCELL( _EQ004 $  VCC);
  _EQ004 = !B & !CLR & !D &  _X006
         # !A & !C & !CLR & !D
         # !D1 &  _X007;
  _X006  = EXP( A &  C);
  _X007  = EXP(!A & !B & !C & !CLR);

-- Node name is 'SPEAKER' 
-- Equation name is 'SPEAKER', location is LC032, type is output.
 SPEAKER = LCELL( _EQ005 $ !CLR);
  _EQ005 = !CLR & !_LC012 &  _X008;
  _X008  = EXP( A & !B & !C & !D);

-- Node name is 'STATES0' 
-- Equation name is 'STATES0', location is LC031, type is output.
 STATES0 = LCELL( _EQ006 $ !CLR);
  _EQ006 = !CLR & !_LC008 &  _X008;
  _X008  = EXP( A & !B & !C & !D);

-- Node name is 'STATES1' 
-- Equation name is 'STATES1', location is LC028, type is output.
 STATES1 = LCELL( _EQ007 $  GND);
  _EQ007 = !CLR &  _LC004 &  _X008;
  _X008  = EXP( A & !B & !C & !D);

-- Node name is 'STATES2' 
-- Equation name is 'STATES2', location is LC027, type is output.
 STATES2 = LCELL( _EQ008 $  GND);
  _EQ008 = !CLR &  _LC023 &  _X008;
  _X008  = EXP( A & !B & !C & !D);

-- Node name is 'STATES3' 
-- Equation name is 'STATES3', location is LC026, type is output.
 STATES3 = LCELL( _EQ009 $  GND);
  _EQ009 = !CLR &  _LC022 &  _X008;
  _X008  = EXP( A & !B & !C & !D);

-- Node name is '~376~1' 
-- Equation name is '~376~1', location is LC022, type is buried.
-- synthesized logic cell 
_LC022   = LCELL( _EQ010 $  _LC021);
  _EQ010 = !A & !B &  C & !D &  _LC021
         # !A & !B & !C &  D &  _LC021
         # !A &  B & !C & !D &  _LC021;

-- Node name is '~382~1' 
-- Equation name is '~382~1', location is LC021, type is buried.
-- synthesized logic cell 
_LC021   = LCELL( _EQ011 $ !CLR);
  _EQ011 =  A & !B & !C & !CLR & !D
         # !CLR & !_LC022;

-- Node name is '~397~1' 
-- Equation name is '~397~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ012 $  _LC024);
  _EQ012 = !A &  B & !C & !D &  _LC024
         # !A & !B &  C & !D &  _LC024
         # !A & !B & !C &  D & !_LC024;

-- Node name is '~403~1' 
-- Equation name is '~403~1', location is LC024, type is buried.
-- synthesized logic cell 
_LC024   = LCELL( _EQ013 $  GND);
  _EQ013 = !CLR &  _LC023 &  _X008;
  _X008  = EXP( A & !B & !C & !D);

-- Node name is '~418~1' 
-- Equation name is '~418~1', location is LC004, type is buried.
-- synthesized logic cell 
_LC004   = LCELL( _EQ014 $  _LC025);
  _EQ014 = !A & !B & !C &  D &  _LC025
         # !A & !B &  C & !D & !_LC025
         # !A &  B & !C & !D & !_LC025;

-- Node name is '~424~1' 
-- Equation name is '~424~1', location is LC025, type is buried.
-- synthesized logic cell 
_LC025   = LCELL( _EQ015 $  GND);
  _EQ015 = !CLR &  _LC004 &  _X008;
  _X008  = EXP( A & !B & !C & !D);

-- Node name is '~439~1' 
-- Equation name is '~439~1', location is LC008, type is buried.
-- synthesized logic cell 
_LC008   = LCELL( _EQ016 $  _LC029);
  _EQ016 = !A &  B & !C & !D &  _LC029
         # !A & !B & !C &  D &  _LC029
         # !A & !B &  C & !D & !_LC029;

-- Node name is '~445~1' 
-- Equation name is '~445~1', location is LC029, type is buried.
-- synthesized logic cell 
_LC029   = LCELL( _EQ017 $ !CLR);
  _EQ017 = !CLR & !_LC008 &  _X008;
  _X008  = EXP( A & !B & !C & !D);

-- Node name is '~460~1' 
-- Equation name is '~460~1', location is LC012, type is buried.
-- synthesized logic cell 
_LC012   = LCELL( _EQ018 $  _LC030);
  _EQ018 = !A & !B & !C &  D & !_LC030
         # !A & !B &  C & !D & !_LC030
         # !A &  B & !C & !D & !_LC030;

-- Node name is '~466~1' 
-- Equation name is '~466~1', location is LC030, type is buried.
-- synthesized logic cell 
_LC030   = LCELL( _EQ019 $ !CLR);
  _EQ019 = !CLR & !_LC012 &  _X008;
  _X008  = EXP( A & !B & !C & !D);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                            d:\ccw\qdjb.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,813K