yangytp1.txt

Verilog HDL编写的四位数码管动态显示程序,外围电路用CPLD来实现

//数码管动态显示//
module dtxs(clk,s1,dig,seg);
input   [0:0]    clk;
input   [0:0]    s1;
output  [3:0]    dig;
output  [7:0]    seg;

reg     [3:0]    dig_reg;
reg     [7:0]    seg_reg;
reg     [25:0]   count;
reg     [1:0]    chbit;
reg     [1:0]    chw;

assign  dig=dig_reg;
assign  seg=seg_reg;

always  @ (posedge  clk)
begin 
       count=count+1;
end

always  @ (negedge  s1)
begin  
       chbit=chbit+1;
end
//选择不同的扫速//
always  @ (chbit)
begin 
       case(chbit)
       2'b00:chw[1:0]=count[24:23];
       2'b01:chw[1:0]=count[22:21];
       2'b10:chw[1:0]=count[20:19];
       2'b11:chw[1:0]=count[18:17];
       endcase
end
//确定数码管显示的顺序以及内容//
always  @ (chw)
begin  
       case(chw)
       2'b00:dig_reg[3:0]=4'b0111;
       2'b01:dig_reg[3:0]=4'b1011;
       2'b10:dig_reg[3:0]=4'b1101;
       2'b11:dig_reg[3:0]=4'b1110;
       endcase
       case(chw)
       2'b00:seg_reg[7:0]=8'h92;
       2'b01:seg_reg[7:0]=8'h82;
       2'b10:seg_reg[7:0]=8'hf8;
       2'b11:seg_reg[7:0]=8'h80;
       endcase
end

endmodule