ps2tolcd.map.rpt

ps/2键盘输入

; state.SETFUNCTION  ; 1          ; 0              ; 0              ; 0              ; 1                 ; 0           ; 0                ; 0             ; 0                  ; 0           ;
; state.SETCGRAM     ; 1          ; 0              ; 0              ; 1              ; 0                 ; 0           ; 0                ; 0             ; 0                  ; 0           ;
+--------------------+------------+----------------+----------------+----------------+-------------------+-------------+------------------+---------------+--------------------+-------------+


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; data_in_buf[7]                                ;   ;
; data_in_buf[6]                                ;   ;
; data_in_buf[5]                                ;   ;
; data_in_buf[4]                                ;   ;
; data_in_buf[3]                                ;   ;
; data_in_buf[2]                                ;   ;
; data_in_buf[1]                                ;   ;
; data_in_buf[0]                                ;   ;
; Number of user-specified and inferred latches ; 8 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 44    ;
; Number of registers using Synchronous Clear  ; 16    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 9     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 17    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |lcd|clkcnt[14]            ;
; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |lcd|count[0]              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |lcd ;
+----------------+-------------+--------------------------------------+
; Parameter Name ; Value       ; Type                                 ;
+----------------+-------------+--------------------------------------+
; IDLE           ; 00000000000 ; Binary                               ;
; CLEAR          ; 00000000001 ; Binary                               ;
; RETURNCURSOR   ; 00000000010 ; Binary                               ;
; SETMODE        ; 00000000100 ; Binary                               ;
; SWITCHMODE     ; 00000001000 ; Binary                               ;
; SHIFT          ; 00000010000 ; Binary                               ;
; SETFUNCTION    ; 00000100000 ; Binary                               ;
; SETCGRAM       ; 00001000000 ; Binary                               ;
; SETDDRAM       ; 00010000000 ; Binary                               ;
; READFLAG       ; 00100000000 ; Binary                               ;
; WRITERAM       ; 01000000000 ; Binary                               ;
; READRAM        ; 10000000000 ; Binary                               ;
; cur_inc        ; 1           ; Integer                              ;
; cur_dec        ; 0           ; Integer                              ;
; cur_shift      ; 1           ; Integer                              ;
; cur_noshift    ; 0           ; Integer                              ;
; open_display   ; 1           ; Integer                              ;
; open_cur       ; 0           ; Integer                              ;
; blank_cur      ; 0           ; Integer                              ;
; shift_display  ; 1           ; Integer                              ;
; shift_cur      ; 0           ; Integer                              ;
; right_shift    ; 1           ; Integer                              ;
; left_shift     ; 0           ; Integer                              ;
; datawidth8     ; 1           ; Integer                              ;
; datawidth4     ; 0           ; Integer                              ;
; twoline        ; 1           ; Integer                              ;
; oneline        ; 0           ; Integer                              ;
; font5x10       ; 1           ; Integer                              ;
; font5x7        ; 0           ; Integer                              ;
+----------------+-------------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Thu Mar 27 23:33:01 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ps2tolcd -c ps2tolcd
Info: Found 1 design units, including 1 entities, in source file ../SRC/DIV16.v
    Info: Found entity 1: div16
Info: Found 1 design units, including 1 entities, in source file ../SRC/div_256.v
    Info: Found entity 1: div_256
Info: Found 1 design units, including 1 entities, in source file ../SRC/lcd.v
    Info: Found entity 1: lcd
Info: Found 1 design units, including 1 entities, in source file ../SRC/ps2_keyboard.v
    Info: Found entity 1: ps2_keyboard_interface
Info: Found 1 design units, including 1 entities, in source file ps2tolcd.bdf
    Info: Found entity 1: ps2tolcd
Info: Elaborating entity "lcd" for the top level hierarchy
Warning: Verilog HDL assignment warning at lcd.v(66): truncated value with size 32 to match size of target (16)
Warning: Verilog HDL assignment warning at lcd.v(70): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(75): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(82): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(88): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(97): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL Always Construct warning at lcd.v(98): variable "data_in" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL assignment warning at lcd.v(107): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(112): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(114): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(116): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(118): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(120): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(122): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(124): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(127): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(130): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(133): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(135): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at lcd.v(139): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(140): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL Always Construct warning at lcd.v(93): variable "data_in_buf" may not be assigned a new value in every possible path through the Always Construct.  Variable "data_in_buf" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Reduced register "lcd_rw~reg0" with stuck data_in port to stuck value GND
Info: State machine "|lcd|state" contains 10 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|lcd|state"
Info: Encoding result for state machine "|lcd|state"
    Info: Completed encoding using 10 state bits
        Info: Encoded state bit "state.IDLE"
        Info: Encoded state bit "state.WRITERAM"
        Info: Encoded state bit "state.SETDDRAM"
        Info: Encoded state bit "state.SETCGRAM"
        Info: Encoded state bit "state.SETFUNCTION"
        Info: Encoded state bit "state.SHIFT"
        Info: Encoded state bit "state.SWITCHMODE"
        Info: Encoded state bit "state.SETMODE"
        Info: Encoded state bit "state.RETURNCURSOR"
        Info: Encoded state bit "state.CLEAR"
    Info: State "|lcd|state.IDLE" uses code string "0000000000"
    Info: State "|lcd|state.SWITCHMODE" uses code string "1000001000"
    Info: State "|lcd|state.WRITERAM" uses code string "1100000000"
    Info: State "|lcd|state.RETURNCURSOR" uses code string "1000000010"
    Info: State "|lcd|state.SETDDRAM" uses code string "1010000000"
    Info: State "|lcd|state.SETMODE" uses code string "1000000100"
    Info: State "|lcd|state.CLEAR" uses code string "1000000001"
    Info: State "|lcd|state.SHIFT" uses code string "1000010000"
    Info: State "|lcd|state.SETFUNCTION" uses code string "1000100000"
    Info: State "|lcd|state.SETCGRAM" uses code string "1001000000"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "lcd_rw" stuck at GND
Info: Implemented 115 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 11 output pins
    Info: Implemented 94 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings
    Info: Processing ended: Thu Mar 27 23:33:06 2008
    Info: Elapsed time: 00:00:06