ps2tolcd.fit.qmsg

ps/2键盘输入

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "8 unused 3.30 8 0 0 " "Info: Number of I/O pins in group: 8 (unused VREF, 3.30 VCCIO, 8 input, 0 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 4 40 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  40 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 42 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 11 34 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 11 total pin(s) used --  34 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 42 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mclk " "Warning: Node \"mclk\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "mclk" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ps2_clk " "Warning: Node \"ps2_clk\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ps2_clk" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ps2_data " "Warning: Node \"ps2_data\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ps2_data" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "reset " "Warning: Node \"reset\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } }  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.712 ns register register " "Info: Estimated most critical path is register to register delay of 5.712 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[5\] 1 REG LAB_X42_Y21 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X42_Y21; Fanout = 6; REG Node = 'count\[5\]'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { count[5] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.150 ns) + CELL(0.292 ns) 1.442 ns always4~204 2 COMB LAB_X42_Y22 1 " "Info: 2: + IC(1.150 ns) + CELL(0.292 ns) = 1.442 ns; Loc. = LAB_X42_Y22; Fanout = 1; COMB Node = 'always4~204'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.442 ns" { count[5] always4~204 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.590 ns) 2.106 ns always4~205 3 COMB LAB_X42_Y22 3 " "Info: 3: + IC(0.074 ns) + CELL(0.590 ns) = 2.106 ns; Loc. = LAB_X42_Y22; Fanout = 3; COMB Node = 'always4~205'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.664 ns" { always4~204 always4~205 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.114 ns) 2.770 ns LessThan~184 4 COMB LAB_X42_Y22 6 " "Info: 4: + IC(0.550 ns) + CELL(0.114 ns) = 2.770 ns; Loc. = LAB_X42_Y22; Fanout = 6; COMB Node = 'LessThan~184'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.664 ns" { always4~205 LessThan~184 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.603 ns) + CELL(0.114 ns) 3.487 ns Select~1051 5 COMB LAB_X42_Y22 4 " "Info: 5: + IC(0.603 ns) + CELL(0.114 ns) = 3.487 ns; Loc. = LAB_X42_Y22; Fanout = 4; COMB Node = 'Select~1051'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.717 ns" { LessThan~184 Select~1051 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.924 ns) + CELL(0.442 ns) 4.853 ns Select~1057 6 COMB LAB_X42_Y21 1 " "Info: 6: + IC(0.924 ns) + CELL(0.442 ns) = 4.853 ns; Loc. = LAB_X42_Y21; Fanout = 1; COMB Node = 'Select~1057'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.366 ns" { Select~1051 Select~1057 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.309 ns) 5.712 ns data\[1\]~reg0 7 REG LAB_X42_Y21 2 " "Info: 7: + IC(0.550 ns) + CELL(0.309 ns) = 5.712 ns; Loc. = LAB_X42_Y21; Fanout = 2; REG Node = 'data\[1\]~reg0'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.859 ns" { Select~1057 data[1]~reg0 } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 94 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.861 ns 32.58 % " "Info: Total cell delay = 1.861 ns ( 32.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.851 ns 67.42 % " "Info: Total interconnect delay = 3.851 ns ( 67.42 % )" {  } {  } 0}  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "5.712 ns" { count[5] always4~204 always4~205 LessThan~184 Select~1051 Select~1057 data[1]~reg0 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "lcd_rw GND " "Info: Pin lcd_rw has GND driving its datain port" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 4 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd_rw" } } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { lcd_rw } "NODE_NAME" } "" } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" "" { lcd_rw } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 27 23:33:24 2008 " "Info: Processing ended: Thu Mar 27 23:33:24 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Info: Elapsed time: 00:00:15" {  } {  } 0}  } {  } 0}