ps2tolcd.fit.qmsg

ps/2键盘输入

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 27 23:33:09 2008 " "Info: Processing started: Thu Mar 27 23:33:09 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ps2tolcd -c ps2tolcd " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ps2tolcd -c ps2tolcd" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "ps2tolcd EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"ps2tolcd\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "10 21 " "Info: No exact pin location assignment(s) for 10 pins of 21 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rst " "Info: Pin rst not assigned to an exact location on the device" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { rst } "NODE_NAME" } "" } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" "" { rst } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[7\] " "Info: Pin data_in\[7\] not assigned to an exact location on the device" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_in\[7\]" } } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { data_in[7] } "NODE_NAME" } "" } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" "" { data_in[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[6\] " "Info: Pin data_in\[6\] not assigned to an exact location on the device" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_in\[6\]" } } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { data_in[6] } "NODE_NAME" } "" } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" "" { data_in[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[5\] " "Info: Pin data_in\[5\] not assigned to an exact location on the device" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_in\[5\]" } } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { data_in[5] } "NODE_NAME" } "" } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" "" { data_in[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[4\] " "Info: Pin data_in\[4\] not assigned to an exact location on the device" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_in\[4\]" } } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { data_in[4] } "NODE_NAME" } "" } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" "" { data_in[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[2\] " "Info: Pin data_in\[2\] not assigned to an exact location on the device" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_in\[2\]" } } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { data_in[2] } "NODE_NAME" } "" } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" "" { data_in[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[1\] " "Info: Pin data_in\[1\] not assigned to an exact location on the device" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_in\[1\]" } } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { data_in[1] } "NODE_NAME" } "" } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" "" { data_in[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[0\] " "Info: Pin data_in\[0\] not assigned to an exact location on the device" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_in\[0\]" } } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { data_in[0] } "NODE_NAME" } "" } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" "" { data_in[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[3\] " "Info: Pin data_in\[3\] not assigned to an exact location on the device" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "data_in\[3\]" } } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { data_in[3] } "NODE_NAME" } "" } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" "" { data_in[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { clk } "NODE_NAME" } "" } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/ps2tolcd.fld" "" "" { clk } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 29 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 29" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 2 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst Global clock in PIN 28 " "Info: Automatically promoted some destinations of signal \"rst\" to use Global clock in PIN 28" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd_rs~reg0 " "Info: Destination \"lcd_rs~reg0\" may be non-global or may not use global clock" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 94 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data\[0\]~reg0 " "Info: Destination \"data\[0\]~reg0\" may be non-global or may not use global clock" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 94 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data\[1\]~reg0 " "Info: Destination \"data\[1\]~reg0\" may be non-global or may not use global clock" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 94 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data\[2\]~reg0 " "Info: Destination \"data\[2\]~reg0\" may be non-global or may not use global clock" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 94 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data\[3\]~reg0 " "Info: Destination \"data\[3\]~reg0\" may be non-global or may not use global clock" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 94 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data\[4\]~reg0 " "Info: Destination \"data\[4\]~reg0\" may be non-global or may not use global clock" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 94 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data\[5\]~reg0 " "Info: Destination \"data\[5\]~reg0\" may be non-global or may not use global clock" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 94 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data\[6\]~reg0 " "Info: Destination \"data\[6\]~reg0\" may be non-global or may not use global clock" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 94 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "data\[7\]~reg0 " "Info: Destination \"data\[7\]~reg0\" may be non-global or may not use global clock" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 94 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lcd_e~reg0 " "Info: Destination \"lcd_e~reg0\" may be non-global or may not use global clock" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 87 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 2 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clk_int Global clock " "Info: Automatically promoted some destinations of signal \"clk_int\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clk_int " "Info: Destination \"clk_int\" may be non-global or may not use global clock" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 79 -1 0 } }  } 0}  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 79 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clkdiv Global clock " "Info: Automatically promoted some destinations of signal \"clkdiv\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clkdiv " "Info: Destination \"clkdiv\" may be non-global or may not use global clock" {  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 72 -1 0 } }  } 0}  } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 72 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}