📄 ps2tolcd.tan.qmsg
字号:
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "state.SETFUNCTION state.SWITCHMODE clk 930 ps " "Info: Found hold time violation between source pin or register \"state.SETFUNCTION\" and destination pin or register \"state.SWITCHMODE\" for clock \"clk\" (Hold time is 930 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.802 ns + Largest " "Info: + Largest clock skew is 1.802 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 17.168 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 17.168 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { clk } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns clkcnt\[9\] 2 REG LC_X9_Y13_N1 4 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X9_Y13_N1; Fanout = 4; REG Node = 'clkcnt\[9\]'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.965 ns" { clk clkcnt[9] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.530 ns) + CELL(0.590 ns) 5.554 ns reduce_nor~109 3 COMB LC_X8_Y14_N5 1 " "Info: 3: + IC(1.530 ns) + CELL(0.590 ns) = 5.554 ns; Loc. = LC_X8_Y14_N5; Fanout = 1; COMB Node = 'reduce_nor~109'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "2.120 ns" { clkcnt[9] reduce_nor~109 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.399 ns) + CELL(0.442 ns) 6.395 ns reduce_nor~111 4 COMB LC_X8_Y14_N9 2 " "Info: 4: + IC(0.399 ns) + CELL(0.442 ns) = 6.395 ns; Loc. = LC_X8_Y14_N9; Fanout = 2; COMB Node = 'reduce_nor~111'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.841 ns" { reduce_nor~109 reduce_nor~111 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.473 ns) + CELL(0.935 ns) 7.803 ns clkdiv 5 REG LC_X8_Y14_N6 3 " "Info: 5: + IC(0.473 ns) + CELL(0.935 ns) = 7.803 ns; Loc. = LC_X8_Y14_N6; Fanout = 3; REG Node = 'clkdiv'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.408 ns" { reduce_nor~111 clkdiv } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 72 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.128 ns) + CELL(0.935 ns) 12.866 ns clk_int 6 REG LC_X8_Y13_N2 26 " "Info: 6: + IC(4.128 ns) + CELL(0.935 ns) = 12.866 ns; Loc. = LC_X8_Y13_N2; Fanout = 26; REG Node = 'clk_int'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "5.063 ns" { clkdiv clk_int } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 79 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.591 ns) + CELL(0.711 ns) 17.168 ns state.SWITCHMODE 7 REG LC_X43_Y21_N3 3 " "Info: 7: + IC(3.591 ns) + CELL(0.711 ns) = 17.168 ns; Loc. = LC_X43_Y21_N3; Fanout = 3; REG Node = 'state.SWITCHMODE'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "4.302 ns" { clk_int state.SWITCHMODE } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 9 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.017 ns 35.05 % " "Info: Total cell delay = 6.017 ns ( 35.05 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.151 ns 64.95 % " "Info: Total interconnect delay = 11.151 ns ( 64.95 % )" { } { } 0} } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "17.168 ns" { clk clkcnt[9] reduce_nor~109 reduce_nor~111 clkdiv clk_int state.SWITCHMODE } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "17.168 ns" { clk clk~out0 clkcnt[9] reduce_nor~109 reduce_nor~111 clkdiv clk_int state.SWITCHMODE } { 0.0ns 0.0ns 1.03ns 1.53ns 0.399ns 0.473ns 4.128ns 3.591ns } { 0.0ns 1.469ns 0.935ns 0.59ns 0.442ns 0.935ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 15.366 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 15.366 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { clk } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns clkcnt\[6\] 2 REG LC_X9_Y14_N8 4 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X9_Y14_N8; Fanout = 4; REG Node = 'clkcnt\[6\]'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.965 ns" { clk clkcnt[6] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.749 ns) + CELL(0.114 ns) 4.297 ns reduce_nor~108 3 COMB LC_X8_Y14_N8 1 " "Info: 3: + IC(0.749 ns) + CELL(0.114 ns) = 4.297 ns; Loc. = LC_X8_Y14_N8; Fanout = 1; COMB Node = 'reduce_nor~108'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.863 ns" { clkcnt[6] reduce_nor~108 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 4.593 ns reduce_nor~111 4 COMB LC_X8_Y14_N9 2 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 4.593 ns; Loc. = LC_X8_Y14_N9; Fanout = 2; COMB Node = 'reduce_nor~111'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.296 ns" { reduce_nor~108 reduce_nor~111 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.473 ns) + CELL(0.935 ns) 6.001 ns clkdiv 5 REG LC_X8_Y14_N6 3 " "Info: 5: + IC(0.473 ns) + CELL(0.935 ns) = 6.001 ns; Loc. = LC_X8_Y14_N6; Fanout = 3; REG Node = 'clkdiv'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.408 ns" { reduce_nor~111 clkdiv } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 72 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.128 ns) + CELL(0.935 ns) 11.064 ns clk_int 6 REG LC_X8_Y13_N2 26 " "Info: 6: + IC(4.128 ns) + CELL(0.935 ns) = 11.064 ns; Loc. = LC_X8_Y13_N2; Fanout = 26; REG Node = 'clk_int'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "5.063 ns" { clkdiv clk_int } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 79 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.591 ns) + CELL(0.711 ns) 15.366 ns state.SETFUNCTION 7 REG LC_X43_Y21_N9 5 " "Info: 7: + IC(3.591 ns) + CELL(0.711 ns) = 15.366 ns; Loc. = LC_X43_Y21_N9; Fanout = 5; REG Node = 'state.SETFUNCTION'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "4.302 ns" { clk_int state.SETFUNCTION } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 9 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.213 ns 33.93 % " "Info: Total cell delay = 5.213 ns ( 33.93 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.153 ns 66.07 % " "Info: Total interconnect delay = 10.153 ns ( 66.07 % )" { } { } 0} } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "15.366 ns" { clk clkcnt[6] reduce_nor~108 reduce_nor~111 clkdiv clk_int state.SETFUNCTION } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.366 ns" { clk clk~out0 clkcnt[6] reduce_nor~108 reduce_nor~111 clkdiv clk_int state.SETFUNCTION } { 0.0ns 0.0ns 1.03ns 0.749ns 0.182ns 0.473ns 4.128ns 3.591ns } { 0.0ns 1.469ns 0.935ns 0.114ns 0.114ns 0.935ns 0.935ns 0.711ns } } } } 0} } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "17.168 ns" { clk clkcnt[9] reduce_nor~109 reduce_nor~111 clkdiv clk_int state.SWITCHMODE } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "17.168 ns" { clk clk~out0 clkcnt[9] reduce_nor~109 reduce_nor~111 clkdiv clk_int state.SWITCHMODE } { 0.0ns 0.0ns 1.03ns 1.53ns 0.399ns 0.473ns 4.128ns 3.591ns } { 0.0ns 1.469ns 0.935ns 0.59ns 0.442ns 0.935ns 0.935ns 0.711ns } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "15.366 ns" { clk clkcnt[6] reduce_nor~108 reduce_nor~111 clkdiv clk_int state.SETFUNCTION } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.366 ns" { clk clk~out0 clkcnt[6] reduce_nor~108 reduce_nor~111 clkdiv clk_int state.SETFUNCTION } { 0.0ns 0.0ns 1.03ns 0.749ns 0.182ns 0.473ns 4.128ns 3.591ns } { 0.0ns 1.469ns 0.935ns 0.114ns 0.114ns 0.935ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 9 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.663 ns - Shortest register register " "Info: - Shortest register to register delay is 0.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.SETFUNCTION 1 REG LC_X43_Y21_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X43_Y21_N9; Fanout = 5; REG Node = 'state.SETFUNCTION'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { state.SETFUNCTION } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.548 ns) + CELL(0.115 ns) 0.663 ns state.SWITCHMODE 2 REG LC_X43_Y21_N3 3 " "Info: 2: + IC(0.548 ns) + CELL(0.115 ns) = 0.663 ns; Loc. = LC_X43_Y21_N3; Fanout = 3; REG Node = 'state.SWITCHMODE'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.663 ns" { state.SETFUNCTION state.SWITCHMODE } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 9 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 17.35 % " "Info: Total cell delay = 0.115 ns ( 17.35 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.548 ns 82.65 % " "Info: Total interconnect delay = 0.548 ns ( 82.65 % )" { } { } 0} } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.663 ns" { state.SETFUNCTION state.SWITCHMODE } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.663 ns" { state.SETFUNCTION state.SWITCHMODE } { 0.0ns 0.548ns } { 0.0ns 0.115ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 9 -1 0 } } } 0} } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "17.168 ns" { clk clkcnt[9] reduce_nor~109 reduce_nor~111 clkdiv clk_int state.SWITCHMODE } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "17.168 ns" { clk clk~out0 clkcnt[9] reduce_nor~109 reduce_nor~111 clkdiv clk_int state.SWITCHMODE } { 0.0ns 0.0ns 1.03ns 1.53ns 0.399ns 0.473ns 4.128ns 3.591ns } { 0.0ns 1.469ns 0.935ns 0.59ns 0.442ns 0.935ns 0.935ns 0.711ns } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "15.366 ns" { clk clkcnt[6] reduce_nor~108 reduce_nor~111 clkdiv clk_int state.SETFUNCTION } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.366 ns" { clk clk~out0 clkcnt[6] reduce_nor~108 reduce_nor~111 clkdiv clk_int state.SETFUNCTION } { 0.0ns 0.0ns 1.03ns 0.749ns 0.182ns 0.473ns 4.128ns 3.591ns } { 0.0ns 1.469ns 0.935ns 0.114ns 0.114ns 0.935ns 0.935ns 0.711ns } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.663 ns" { state.SETFUNCTION state.SWITCHMODE } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.663 ns" { state.SETFUNCTION state.SWITCHMODE } { 0.0ns 0.548ns } { 0.0ns 0.115ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "clkcnt\[8\] rst clk 1.801 ns register " "Info: tsu for register \"clkcnt\[8\]\" (data pin = \"rst\", clock pin = \"clk\") is 1.801 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.974 ns + Longest pin register " "Info: + Longest pin to register delay is 4.974 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_28 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 39; PIN Node = 'rst'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { rst } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.114 ns) 2.614 ns clkcnt\[14\]~405 2 COMB LC_X8_Y14_N4 16 " "Info: 2: + IC(1.031 ns) + CELL(0.114 ns) = 2.614 ns; Loc. = LC_X8_Y14_N4; Fanout = 16; COMB Node = 'clkcnt\[14\]~405'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.145 ns" { rst clkcnt[14]~405 } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.248 ns) + CELL(1.112 ns) 4.974 ns clkcnt\[8\] 3 REG LC_X9_Y13_N0 4 " "Info: 3: + IC(1.248 ns) + CELL(1.112 ns) = 4.974 ns; Loc. = LC_X9_Y13_N0; Fanout = 4; REG Node = 'clkcnt\[8\]'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "2.360 ns" { clkcnt[14]~405 clkcnt[8] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.695 ns 54.18 % " "Info: Total cell delay = 2.695 ns ( 54.18 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.279 ns 45.82 % " "Info: Total interconnect delay = 2.279 ns ( 45.82 % )" { } { } 0} } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "4.974 ns" { rst clkcnt[14]~405 clkcnt[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.974 ns" { rst rst~out0 clkcnt[14]~405 clkcnt[8] } { 0.000ns 0.000ns 1.031ns 1.248ns } { 0.000ns 1.469ns 0.114ns 1.112ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.210 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.210 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { clk } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.711 ns) 3.210 ns clkcnt\[8\] 2 REG LC_X9_Y13_N0 4 " "Info: 2: + IC(1.030 ns) + CELL(0.711 ns) = 3.210 ns; Loc. = LC_X9_Y13_N0; Fanout = 4; REG Node = 'clkcnt\[8\]'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.741 ns" { clk clkcnt[8] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 67.91 % " "Info: Total cell delay = 2.180 ns ( 67.91 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.030 ns 32.09 % " "Info: Total interconnect delay = 1.030 ns ( 32.09 % )" { } { } 0} } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "3.210 ns" { clk clkcnt[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.210 ns" { clk clk~out0 clkcnt[8] } { 0.000ns 0.000ns 1.030ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "4.974 ns" { rst clkcnt[14]~405 clkcnt[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.974 ns" { rst rst~out0 clkcnt[14]~405 clkcnt[8] } { 0.000ns 0.000ns 1.031ns 1.248ns } { 0.000ns 1.469ns 0.114ns 1.112ns } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "3.210 ns" { clk clkcnt[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.210 ns" { clk clk~out0 clkcnt[8] } { 0.000ns 0.000ns 1.030ns } { 0.000ns 1.469ns 0.711ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk lcd_rs lcd_rs~reg0 23.326 ns register " "Info: tco from clock \"clk\" to destination pin \"lcd_rs\" through register \"lcd_rs~reg0\" is 23.326 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 17.168 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 17.168 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { clk } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns clkcnt\[9\] 2 REG LC_X9_Y13_N1 4 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X9_Y13_N1; Fanout = 4; REG Node = 'clkcnt\[9\]'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.965 ns" { clk clkcnt[9] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.530 ns) + CELL(0.590 ns) 5.554 ns reduce_nor~109 3 COMB LC_X8_Y14_N5 1 " "Info: 3: + IC(1.530 ns) + CELL(0.590 ns) = 5.554 ns; Loc. = LC_X8_Y14_N5; Fanout = 1; COMB Node = 'reduce_nor~109'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "2.120 ns" { clkcnt[9] reduce_nor~109 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.399 ns) + CELL(0.442 ns) 6.395 ns reduce_nor~111 4 COMB LC_X8_Y14_N9 2 " "Info: 4: + IC(0.399 ns) + CELL(0.442 ns) = 6.395 ns; Loc. = LC_X8_Y14_N9; Fanout = 2; COMB Node = 'reduce_nor~111'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.841 ns" { reduce_nor~109 reduce_nor~111 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.473 ns) + CELL(0.935 ns) 7.803 ns clkdiv 5 REG LC_X8_Y14_N6 3 " "Info: 5: + IC(0.473 ns) + CELL(0.935 ns) = 7.803 ns; Loc. = LC_X8_Y14_N6; Fanout = 3; REG Node = 'clkdiv'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO ⌨️ 快捷键说明
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