📄 ps2tolcd.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "22 " "Warning: Found 22 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[15\] " "Info: Detected ripple clock \"clkcnt\[15\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[15\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[12\] " "Info: Detected ripple clock \"clkcnt\[12\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[12\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[14\] " "Info: Detected ripple clock \"clkcnt\[14\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[14\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[13\] " "Info: Detected ripple clock \"clkcnt\[13\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[13\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[11\] " "Info: Detected ripple clock \"clkcnt\[11\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[11\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[10\] " "Info: Detected ripple clock \"clkcnt\[10\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[10\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[9\] " "Info: Detected ripple clock \"clkcnt\[9\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[9\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[8\] " "Info: Detected ripple clock \"clkcnt\[8\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[8\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[6\] " "Info: Detected ripple clock \"clkcnt\[6\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[6\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[7\] " "Info: Detected ripple clock \"clkcnt\[7\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[7\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[5\] " "Info: Detected ripple clock \"clkcnt\[5\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[5\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[4\] " "Info: Detected ripple clock \"clkcnt\[4\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[4\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[3\] " "Info: Detected ripple clock \"clkcnt\[3\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[3\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[2\] " "Info: Detected ripple clock \"clkcnt\[2\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[2\]" } } } } } 0} { "Info" "ITAN_GATED_CLK" "reduce_nor~108 " "Info: Detected gated clock \"reduce_nor~108\" as buffer" { } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reduce_nor~108" } } } } } 0} { "Info" "ITAN_GATED_CLK" "reduce_nor~110 " "Info: Detected gated clock \"reduce_nor~110\" as buffer" { } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reduce_nor~110" } } } } } 0} { "Info" "ITAN_GATED_CLK" "reduce_nor~109 " "Info: Detected gated clock \"reduce_nor~109\" as buffer" { } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reduce_nor~109" } } } } } 0} { "Info" "ITAN_GATED_CLK" "reduce_nor~107 " "Info: Detected gated clock \"reduce_nor~107\" as buffer" { } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reduce_nor~107" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[1\] " "Info: Detected ripple clock \"clkcnt\[1\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[1\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[0\] " "Info: Detected ripple clock \"clkcnt\[0\]\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[0\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clk_int " "Info: Detected ripple clock \"clk_int\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 79 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_int" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clkdiv " "Info: Detected ripple clock \"clkdiv\" as buffer" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 72 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkdiv" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[5\] register data\[1\]~reg0 118.75 MHz 8.421 ns Internal " "Info: Clock \"clk\" has Internal fmax of 118.75 MHz between source register \"count\[5\]\" and destination register \"data\[1\]~reg0\" (period= 8.421 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.358 ns + Longest register register " "Info: + Longest register to register delay is 6.358 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[5\] 1 REG LC_X42_Y21_N7 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X42_Y21_N7; Fanout = 6; REG Node = 'count\[5\]'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { count[5] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.302 ns) + CELL(0.292 ns) 1.594 ns always4~204 2 COMB LC_X42_Y22_N1 1 " "Info: 2: + IC(1.302 ns) + CELL(0.292 ns) = 1.594 ns; Loc. = LC_X42_Y22_N1; Fanout = 1; COMB Node = 'always4~204'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.594 ns" { count[5] always4~204 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.114 ns) 2.136 ns always4~205 3 COMB LC_X42_Y22_N0 3 " "Info: 3: + IC(0.428 ns) + CELL(0.114 ns) = 2.136 ns; Loc. = LC_X42_Y22_N0; Fanout = 3; COMB Node = 'always4~205'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.542 ns" { always4~204 always4~205 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.467 ns) + CELL(0.114 ns) 2.717 ns LessThan~184 4 COMB LC_X42_Y22_N5 6 " "Info: 4: + IC(0.467 ns) + CELL(0.114 ns) = 2.717 ns; Loc. = LC_X42_Y22_N5; Fanout = 6; COMB Node = 'LessThan~184'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.581 ns" { always4~205 LessThan~184 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.442 ns) 3.585 ns Select~1051 5 COMB LC_X42_Y22_N2 4 " "Info: 5: + IC(0.426 ns) + CELL(0.442 ns) = 3.585 ns; Loc. = LC_X42_Y22_N2; Fanout = 4; COMB Node = 'Select~1051'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.868 ns" { LessThan~184 Select~1051 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.288 ns) + CELL(0.292 ns) 5.165 ns Select~1057 6 COMB LC_X42_Y21_N2 1 " "Info: 6: + IC(1.288 ns) + CELL(0.292 ns) = 5.165 ns; Loc. = LC_X42_Y21_N2; Fanout = 1; COMB Node = 'Select~1057'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.580 ns" { Select~1051 Select~1057 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.738 ns) 6.358 ns data\[1\]~reg0 7 REG LC_X42_Y21_N3 2 " "Info: 7: + IC(0.455 ns) + CELL(0.738 ns) = 6.358 ns; Loc. = LC_X42_Y21_N3; Fanout = 2; REG Node = 'data\[1\]~reg0'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.193 ns" { Select~1057 data[1]~reg0 } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 94 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.992 ns 31.33 % " "Info: Total cell delay = 1.992 ns ( 31.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.366 ns 68.67 % " "Info: Total interconnect delay = 4.366 ns ( 68.67 % )" { } { } 0} } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "6.358 ns" { count[5] always4~204 always4~205 LessThan~184 Select~1051 Select~1057 data[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.358 ns" { count[5] always4~204 always4~205 LessThan~184 Select~1051 Select~1057 data[1]~reg0 } { 0.000ns 1.302ns 0.428ns 0.467ns 0.426ns 1.288ns 0.455ns } { 0.000ns 0.292ns 0.114ns 0.114ns 0.442ns 0.292ns 0.738ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.802 ns - Smallest " "Info: - Smallest clock skew is -1.802 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 15.366 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 15.366 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { clk } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns clkcnt\[6\] 2 REG LC_X9_Y14_N8 4 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X9_Y14_N8; Fanout = 4; REG Node = 'clkcnt\[6\]'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.965 ns" { clk clkcnt[6] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.749 ns) + CELL(0.114 ns) 4.297 ns reduce_nor~108 3 COMB LC_X8_Y14_N8 1 " "Info: 3: + IC(0.749 ns) + CELL(0.114 ns) = 4.297 ns; Loc. = LC_X8_Y14_N8; Fanout = 1; COMB Node = 'reduce_nor~108'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.863 ns" { clkcnt[6] reduce_nor~108 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 4.593 ns reduce_nor~111 4 COMB LC_X8_Y14_N9 2 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 4.593 ns; Loc. = LC_X8_Y14_N9; Fanout = 2; COMB Node = 'reduce_nor~111'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.296 ns" { reduce_nor~108 reduce_nor~111 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.473 ns) + CELL(0.935 ns) 6.001 ns clkdiv 5 REG LC_X8_Y14_N6 3 " "Info: 5: + IC(0.473 ns) + CELL(0.935 ns) = 6.001 ns; Loc. = LC_X8_Y14_N6; Fanout = 3; REG Node = 'clkdiv'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.408 ns" { reduce_nor~111 clkdiv } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 72 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.128 ns) + CELL(0.935 ns) 11.064 ns clk_int 6 REG LC_X8_Y13_N2 26 " "Info: 6: + IC(4.128 ns) + CELL(0.935 ns) = 11.064 ns; Loc. = LC_X8_Y13_N2; Fanout = 26; REG Node = 'clk_int'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "5.063 ns" { clkdiv clk_int } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 79 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.591 ns) + CELL(0.711 ns) 15.366 ns data\[1\]~reg0 7 REG LC_X42_Y21_N3 2 " "Info: 7: + IC(3.591 ns) + CELL(0.711 ns) = 15.366 ns; Loc. = LC_X42_Y21_N3; Fanout = 2; REG Node = 'data\[1\]~reg0'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "4.302 ns" { clk_int data[1]~reg0 } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 94 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.213 ns 33.93 % " "Info: Total cell delay = 5.213 ns ( 33.93 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.153 ns 66.07 % " "Info: Total interconnect delay = 10.153 ns ( 66.07 % )" { } { } 0} } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "15.366 ns" { clk clkcnt[6] reduce_nor~108 reduce_nor~111 clkdiv clk_int data[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.366 ns" { clk clk~out0 clkcnt[6] reduce_nor~108 reduce_nor~111 clkdiv clk_int data[1]~reg0 } { 0.000ns 0.000ns 1.030ns 0.749ns 0.182ns 0.473ns 4.128ns 3.591ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.114ns 0.935ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 17.168 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 17.168 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'clk'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "" { clk } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns clkcnt\[9\] 2 REG LC_X9_Y13_N1 4 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X9_Y13_N1; Fanout = 4; REG Node = 'clkcnt\[9\]'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.965 ns" { clk clkcnt[9] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 56 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.530 ns) + CELL(0.590 ns) 5.554 ns reduce_nor~109 3 COMB LC_X8_Y14_N5 1 " "Info: 3: + IC(1.530 ns) + CELL(0.590 ns) = 5.554 ns; Loc. = LC_X8_Y14_N5; Fanout = 1; COMB Node = 'reduce_nor~109'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "2.120 ns" { clkcnt[9] reduce_nor~109 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.399 ns) + CELL(0.442 ns) 6.395 ns reduce_nor~111 4 COMB LC_X8_Y14_N9 2 " "Info: 4: + IC(0.399 ns) + CELL(0.442 ns) = 6.395 ns; Loc. = LC_X8_Y14_N9; Fanout = 2; COMB Node = 'reduce_nor~111'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "0.841 ns" { reduce_nor~109 reduce_nor~111 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.473 ns) + CELL(0.935 ns) 7.803 ns clkdiv 5 REG LC_X8_Y14_N6 3 " "Info: 5: + IC(0.473 ns) + CELL(0.935 ns) = 7.803 ns; Loc. = LC_X8_Y14_N6; Fanout = 3; REG Node = 'clkdiv'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "1.408 ns" { reduce_nor~111 clkdiv } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 72 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.128 ns) + CELL(0.935 ns) 12.866 ns clk_int 6 REG LC_X8_Y13_N2 26 " "Info: 6: + IC(4.128 ns) + CELL(0.935 ns) = 12.866 ns; Loc. = LC_X8_Y13_N2; Fanout = 26; REG Node = 'clk_int'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "5.063 ns" { clkdiv clk_int } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 79 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.591 ns) + CELL(0.711 ns) 17.168 ns count\[5\] 7 REG LC_X42_Y21_N7 6 " "Info: 7: + IC(3.591 ns) + CELL(0.711 ns) = 17.168 ns; Loc. = LC_X42_Y21_N7; Fanout = 6; REG Node = 'count\[5\]'" { } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "4.302 ns" { clk_int count[5] } "NODE_NAME" } "" } } { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.017 ns 35.05 % " "Info: Total cell delay = 6.017 ns ( 35.05 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.151 ns 64.95 % " "Info: Total interconnect delay = 11.151 ns ( 64.95 % )" { } { } 0} } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "17.168 ns" { clk clkcnt[9] reduce_nor~109 reduce_nor~111 clkdiv clk_int count[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "17.168 ns" { clk clk~out0 clkcnt[9] reduce_nor~109 reduce_nor~111 clkdiv clk_int count[5] } { 0.000ns 0.000ns 1.030ns 1.530ns 0.399ns 0.473ns 4.128ns 3.591ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.442ns 0.935ns 0.935ns 0.711ns } } } } 0} } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "15.366 ns" { clk clkcnt[6] reduce_nor~108 reduce_nor~111 clkdiv clk_int data[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.366 ns" { clk clk~out0 clkcnt[6] reduce_nor~108 reduce_nor~111 clkdiv clk_int data[1]~reg0 } { 0.000ns 0.000ns 1.030ns 0.749ns 0.182ns 0.473ns 4.128ns 3.591ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.114ns 0.935ns 0.935ns 0.711ns } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "17.168 ns" { clk clkcnt[9] reduce_nor~109 reduce_nor~111 clkdiv clk_int count[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "17.168 ns" { clk clk~out0 clkcnt[9] reduce_nor~109 reduce_nor~111 clkdiv clk_int count[5] } { 0.000ns 0.000ns 1.030ns 1.530ns 0.399ns 0.473ns 4.128ns 3.591ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.442ns 0.935ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 11 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "../SRC/lcd.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/SRC/lcd.v" 94 -1 0 } } } 0} } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "6.358 ns" { count[5] always4~204 always4~205 LessThan~184 Select~1051 Select~1057 data[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.358 ns" { count[5] always4~204 always4~205 LessThan~184 Select~1051 Select~1057 data[1]~reg0 } { 0.000ns 1.302ns 0.428ns 0.467ns 0.426ns 1.288ns 0.455ns } { 0.000ns 0.292ns 0.114ns 0.114ns 0.442ns 0.292ns 0.738ns } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "15.366 ns" { clk clkcnt[6] reduce_nor~108 reduce_nor~111 clkdiv clk_int data[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.366 ns" { clk clk~out0 clkcnt[6] reduce_nor~108 reduce_nor~111 clkdiv clk_int data[1]~reg0 } { 0.000ns 0.000ns 1.030ns 0.749ns 0.182ns 0.473ns 4.128ns 3.591ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.114ns 0.935ns 0.935ns 0.711ns } } } { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd_cmp.qrpt" Compiler "ps2tolcd" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/db/ps2tolcd.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/PS2_LCD/PROJ/" "" "17.168 ns" { clk clkcnt[9] reduce_nor~109 reduce_nor~111 clkdiv clk_int count[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "17.168 ns" { clk clk~out0 clkcnt[9] reduce_nor~109 reduce_nor~111 clkdiv clk_int count[5] } { 0.000ns 0.000ns 1.030ns 1.530ns 0.399ns 0.473ns 4.128ns 3.591ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.442ns 0.935ns 0.935ns 0.711ns } } } } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 22 " "Warning: Circuit may not operate. Detected 22 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0}
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