ps2_keyboard_interface.fit.qmsg

实现PS/2接口与RS-232接口的数据传输

{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "6 unused 3.30 1 5 0 " "Info: Number of I/O pins in group: 6 (unused VREF, 3.30 VCCIO, 1 input, 5 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 2 42 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  42 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 1 41 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  41 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 8 37 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 8 total pin(s) used --  37 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 42 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.929 ns register register " "Info: Estimated most critical path is register to register delay of 1.929 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[6\] 1 REG LAB_X30_Y13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X30_Y13; Fanout = 1; REG Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[6\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "" { uart_if:inst3|uart:U1|txmit:u2|tbr[6] } "NODE_NAME" } "" } } { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.738 ns) 1.929 ns uart_if:inst3\|uart:U1\|txmit:u2\|tsr\[6\] 2 REG LAB_X26_Y12 2 " "Info: 2: + IC(1.191 ns) + CELL(0.738 ns) = 1.929 ns; Loc. = LAB_X26_Y12; Fanout = 2; REG Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|tsr\[6\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "1.929 ns" { uart_if:inst3|uart:U1|txmit:u2|tbr[6] uart_if:inst3|uart:U1|txmit:u2|tsr[6] } "NODE_NAME" } "" } } { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns 38.26 % " "Info: Total cell delay = 0.738 ns ( 38.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.191 ns 61.74 % " "Info: Total interconnect delay = 1.191 ns ( 61.74 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "1.929 ns" { uart_if:inst3|uart:U1|txmit:u2|tbr[6] uart_if:inst3|uart:U1|txmit:u2|tsr[6] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 4 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 4%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "1 " "Warning: The following 1 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ps2_clk a permanently enabled " "Info: Pin ps2_clk has a permanently enabled output enable" {  } { { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 80 784 960 96 "ps2_clk" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ps2_clk" } } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "" { ps2_clk } "NODE_NAME" } "" } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard_interface.fld" "" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard_interface.fld" "" "" { ps2_clk } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: The following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_write GND " "Info: Pin tx_write has GND driving its datain port" {  } { { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 208 800 976 224 "tx_write" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "tx_write" } } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "" { tx_write } "NODE_NAME" } "" } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard_interface.fld" "" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard_interface.fld" "" "" { tx_write } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "rx_ascii\[7\] GND " "Info: Pin rx_ascii\[7\] has GND driving its datain port" {  } { { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 176 792 968 192 "rx_ascii\[7..0\]" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rx_ascii\[7\]" } } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "" { rx_ascii[7] } "NODE_NAME" } "" } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard_interface.fld" "" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard_interface.fld" "" "" { rx_ascii[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ps2_clk VCC " "Info: Pin ps2_clk has VCC driving its datain port" {  } { { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 80 784 960 96 "ps2_clk" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ps2_clk" } } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "" { ps2_clk } "NODE_NAME" } "" } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard_interface.fld" "" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard_interface.fld" "" "" { ps2_clk } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: The following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "ps2_keyboard_interface:inst\|ps2_data_hi_z~29 " "Info: The following pins have the same output enable: ps2_keyboard_interface:inst\|ps2_data_hi_z~29" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional ps2_data LVTTL " "Info: Type bidirectional pin ps2_data uses the LVTTL I/O standard" {  } { { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 96 784 960 112 "ps2_data" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ps2_data" } } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "" { ps2_data } "NODE_NAME" } "" } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard_interface.fld" "" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard_interface.fld" "" "" { ps2_data } "NODE_NAME" } }  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 14 22:29:38 2006 " "Info: Processing ended: Thu Sep 14 22:29:38 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Info: Elapsed time: 00:00:19" {  } {  } 0}  } {  } 0}