ps2_keyboard_interface.map.qmsg

实现PS/2接口与RS-232接口的数据传输

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_if.v(69) " "Warning: Verilog HDL assignment warning at uart_if.v(69): truncated value with size 32 to match size of target (1)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 69 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 uart_if.v(70) " "Warning: Verilog HDL assignment warning at uart_if.v(70): truncated value with size 32 to match size of target (8)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 70 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 uart_if.v(71) " "Warning: Verilog HDL assignment warning at uart_if.v(71): truncated value with size 32 to match size of target (8)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 71 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_if.v(72) " "Warning: Verilog HDL assignment warning at uart_if.v(72): truncated value with size 32 to match size of target (1)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 72 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_if.v(78) " "Warning: Verilog HDL assignment warning at uart_if.v(78): truncated value with size 32 to match size of target (1)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 78 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_if.v(82) " "Warning: Verilog HDL assignment warning at uart_if.v(82): truncated value with size 32 to match size of target (1)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 82 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 uart_if.v(85) " "Warning: Verilog HDL assignment warning at uart_if.v(85): truncated value with size 32 to match size of target (8)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 85 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_if.v(91) " "Warning: Verilog HDL assignment warning at uart_if.v(91): truncated value with size 32 to match size of target (1)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 91 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_if.v(101) " "Warning: Verilog HDL assignment warning at uart_if.v(101): truncated value with size 32 to match size of target (1)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 101 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_if.v(102) " "Warning: Verilog HDL assignment warning at uart_if.v(102): truncated value with size 32 to match size of target (1)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 102 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_if.v(103) " "Warning: Verilog HDL assignment warning at uart_if.v(103): truncated value with size 32 to match size of target (1)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 103 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_if.v(108) " "Warning: Verilog HDL assignment warning at uart_if.v(108): truncated value with size 32 to match size of target (1)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 108 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_if.v(114) " "Warning: Verilog HDL assignment warning at uart_if.v(114): truncated value with size 32 to match size of target (1)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 114 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_if.v(125) " "Warning: Verilog HDL assignment warning at uart_if.v(125): truncated value with size 32 to match size of target (1)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 125 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_if.v(130) " "Warning: Verilog HDL assignment warning at uart_if.v(130): truncated value with size 32 to match size of target (1)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 130 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_if.v(135) " "Warning: Verilog HDL assignment warning at uart_if.v(135): truncated value with size 32 to match size of target (1)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 135 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart uart_if:inst3\|uart:U1 " "Info: Elaborating entity \"uart\" for hierarchy \"uart_if:inst3\|uart:U1\"" {  } { { "../src/ref2/uart_if.v" "U1" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 43 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rcvr uart_if:inst3\|uart:U1\|rcvr:u1 " "Info: Elaborating entity \"rcvr\" for hierarchy \"uart_if:inst3\|uart:U1\|rcvr:u1\"" {  } { { "../src/ref2/uart.v" "u1" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart.v" 29 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 rcvr.v(92) " "Warning: Verilog HDL assignment warning at rcvr.v(92): truncated value with size 32 to match size of target (4)" {  } { { "../src/ref2/rcvr.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/rcvr.v" 92 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 rcvr.v(134) " "Warning: Verilog HDL assignment warning at rcvr.v(134): truncated value with size 32 to match size of target (4)" {  } { { "../src/ref2/rcvr.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/rcvr.v" 134 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "txmit uart_if:inst3\|uart:U1\|txmit:u2 " "Info: Elaborating entity \"txmit\" for hierarchy \"uart_if:inst3\|uart:U1\|txmit:u2\"" {  } { { "../src/ref2/uart.v" "u2" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart.v" 31 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 txmit.v(86) " "Warning: Verilog HDL assignment warning at txmit.v(86): truncated value with size 32 to match size of target (4)" {  } { { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 86 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 txmit.v(147) " "Warning: Verilog HDL assignment warning at txmit.v(147): truncated value with size 32 to match size of target (4)" {  } { { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 147 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_4 div_4:inst2 " "Info: Elaborating entity \"div_4\" for hierarchy \"div_4:inst2\"" {  } { { "ps2_keyboard.bdf" "inst2" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 336 200 328 432 "inst2" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 div_4.v(8) " "Warning: Verilog HDL assignment warning at div_4.v(8): truncated value with size 32 to match size of target (13)" {  } { { "../src/ref2/div_4.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/div_4.v" 8 0 0 } }  } 0}