ps2_keyboard_interface.map.qmsg

实现PS/2接口与RS-232接口的数据传输

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 14 22:28:57 2006 " "Info: Processing started: Thu Sep 14 22:28:57 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off KEYBAORD -c ps2_keyboard_interface " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off KEYBAORD -c ps2_keyboard_interface" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/ref2/div_4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../src/ref2/div_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_4 " "Info: Found entity 1: div_4" {  } { { "../src/ref2/div_4.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/div_4.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "rcvr.v(50) " "Warning: (10273) Verilog HDL warning at rcvr.v(50): extended using \"x\" or \"z\"" {  } { { "../src/ref2/rcvr.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/rcvr.v" 50 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "rcvr.v(97) " "Warning: (10268) Verilog HDL information at rcvr.v(97): Always Construct contains both blocking and non-blocking assignments" {  } { { "../src/ref2/rcvr.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/rcvr.v" 97 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/ref2/rcvr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../src/ref2/rcvr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rcvr " "Info: Found entity 1: rcvr" {  } { { "../src/ref2/rcvr.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/rcvr.v" 23 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/ref2/txmit.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../src/ref2/txmit.v" { { "Info" "ISGN_ENTITY_NAME" "1 txmit " "Info: Found entity 1: txmit" {  } { { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 13 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/ref2/uart.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../src/ref2/uart.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart " "Info: Found entity 1: uart" {  } { { "../src/ref2/uart.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart.v" 13 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/ref2/uart_if.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../src/ref2/uart_if.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_if " "Info: Found entity 1: uart_if" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div_256.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file div_256.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_256 " "Info: Found entity 1: div_256" {  } { { "div_256.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/div_256.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ps2_keyboard.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ps2_keyboard.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Info: Found entity 1: ps2_keyboard" {  } { { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../Src/ref2/ps2_keyboard.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../Src/ref2/ps2_keyboard.v" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard_interface " "Info: Found entity 1: ps2_keyboard_interface" {  } { { "../Src/ref2/ps2_keyboard.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Src/ref2/ps2_keyboard.v" 123 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_buf.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file data_buf.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_buf " "Info: Found entity 1: data_buf" {  } { { "data_buf.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/data_buf.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ps2_keyboard " "Info: Elaborating entity \"ps2_keyboard\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "tx_write ps2_keyboard_interface inst " "Warning: Port \"tx_write\" of type ps2_keyboard_interface and instance \"inst\" is missing source signal" {  } { { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 56 488 736 280 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "tx_data ps2_keyboard_interface inst " "Warning: Port \"tx_data\" of type ps2_keyboard_interface and instance \"inst\" is missing source signal" {  } { { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 56 488 736 280 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "rxd uart_if inst3 " "Warning: Port \"rxd\" of type uart_if and instance \"inst3\" is missing source signal" {  } { { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 336 512 696 464 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_if uart_if:inst3 " "Info: Elaborating entity \"uart_if\" for hierarchy \"uart_if:inst3\"" {  } { { "ps2_keyboard.bdf" "inst3" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 336 512 696 464 "inst3" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 uart_if.v(49) " "Warning: Verilog HDL assignment warning at uart_if.v(49): truncated value with size 32 to match size of target (4)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 uart_if.v(51) " "Warning: Verilog HDL assignment warning at uart_if.v(51): truncated value with size 32 to match size of target (4)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 51 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 uart_if.v(61) " "Warning: Verilog HDL assignment warning at uart_if.v(61): truncated value with size 32 to match size of target (8)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 61 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 uart_if.v(62) " "Warning: Verilog HDL assignment warning at uart_if.v(62): truncated value with size 32 to match size of target (8)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 62 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 uart_if.v(63) " "Warning: Verilog HDL assignment warning at uart_if.v(63): truncated value with size 32 to match size of target (8)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 63 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_if.v(64) " "Warning: Verilog HDL assignment warning at uart_if.v(64): truncated value with size 32 to match size of target (1)" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 64 0 0 } }  } 0}