ps2_keyboard_interface.tan.qmsg

实现PS/2接口与RS-232接口的数据传输

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "mclk 42 " "Warning: Circuit may not operate. Detected 42 non-operational path(s) clocked by clock \"mclk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "data_buf:inst4\|data_in_buf\[3\]~reg0 uart_if:inst3\|din\[3\] mclk 3.239 ns " "Info: Found hold time violation between source  pin or register \"data_buf:inst4\|data_in_buf\[3\]~reg0\" and destination pin or register \"uart_if:inst3\|din\[3\]\" for clock \"mclk\" (Hold time is 3.239 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.853 ns + Largest " "Info: + Largest clock skew is 4.853 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 12.579 ns + Longest register " "Info: + Longest clock path from clock \"mclk\" to destination register is 12.579 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_153 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 21; CLK Node = 'mclk'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 72 24 192 88 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns div_4:inst2\|acc\[12\] 2 REG LC_X8_Y13_N6 31 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N6; Fanout = 31; REG Node = 'div_4:inst2\|acc\[12\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "1.965 ns" { mclk div_4:inst2|acc[12] } "NODE_NAME" } "" } } { "../src/ref2/div_4.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/div_4.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.580 ns) + CELL(0.935 ns) 7.949 ns uart_if:inst3\|cnt\[3\] 3 REG LC_X44_Y13_N5 30 " "Info: 3: + IC(3.580 ns) + CELL(0.935 ns) = 7.949 ns; Loc. = LC_X44_Y13_N5; Fanout = 30; REG Node = 'uart_if:inst3\|cnt\[3\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "4.515 ns" { div_4:inst2|acc[12] uart_if:inst3|cnt[3] } "NODE_NAME" } "" } } { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.919 ns) + CELL(0.711 ns) 12.579 ns uart_if:inst3\|din\[3\] 4 REG LC_X45_Y13_N1 1 " "Info: 4: + IC(3.919 ns) + CELL(0.711 ns) = 12.579 ns; Loc. = LC_X45_Y13_N1; Fanout = 1; REG Node = 'uart_if:inst3\|din\[3\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "4.630 ns" { uart_if:inst3|cnt[3] uart_if:inst3|din[3] } "NODE_NAME" } "" } } { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns 32.20 % " "Info: Total cell delay = 4.050 ns ( 32.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.529 ns 67.80 % " "Info: Total interconnect delay = 8.529 ns ( 67.80 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "12.579 ns" { mclk div_4:inst2|acc[12] uart_if:inst3|cnt[3] uart_if:inst3|din[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.579 ns" { mclk mclk~out0 div_4:inst2|acc[12] uart_if:inst3|cnt[3] uart_if:inst3|din[3] } { 0.0ns 0.0ns 1.03ns 3.58ns 3.919ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 7.726 ns - Shortest register " "Info: - Shortest clock path from clock \"mclk\" to source register is 7.726 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_153 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 21; CLK Node = 'mclk'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 72 24 192 88 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns div_4:inst2\|acc\[12\] 2 REG LC_X8_Y13_N6 31 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N6; Fanout = 31; REG Node = 'div_4:inst2\|acc\[12\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "1.965 ns" { mclk div_4:inst2|acc[12] } "NODE_NAME" } "" } } { "../src/ref2/div_4.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/div_4.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.581 ns) + CELL(0.711 ns) 7.726 ns data_buf:inst4\|data_in_buf\[3\]~reg0 3 REG LC_X45_Y15_N3 1 " "Info: 3: + IC(3.581 ns) + CELL(0.711 ns) = 7.726 ns; Loc. = LC_X45_Y15_N3; Fanout = 1; REG Node = 'data_buf:inst4\|data_in_buf\[3\]~reg0'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "4.292 ns" { div_4:inst2|acc[12] data_buf:inst4|data_in_buf[3]~reg0 } "NODE_NAME" } "" } } { "data_buf.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/data_buf.v" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 40.32 % " "Info: Total cell delay = 3.115 ns ( 40.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.611 ns 59.68 % " "Info: Total interconnect delay = 4.611 ns ( 59.68 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "7.726 ns" { mclk div_4:inst2|acc[12] data_buf:inst4|data_in_buf[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.726 ns" { mclk mclk~out0 div_4:inst2|acc[12] data_buf:inst4|data_in_buf[3]~reg0 } { 0.0ns 0.0ns 1.03ns 3.581ns } { 0.0ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "12.579 ns" { mclk div_4:inst2|acc[12] uart_if:inst3|cnt[3] uart_if:inst3|din[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.579 ns" { mclk mclk~out0 div_4:inst2|acc[12] uart_if:inst3|cnt[3] uart_if:inst3|din[3] } { 0.0ns 0.0ns 1.03ns 3.58ns 3.919ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "7.726 ns" { mclk div_4:inst2|acc[12] data_buf:inst4|data_in_buf[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.726 ns" { mclk mclk~out0 div_4:inst2|acc[12] data_buf:inst4|data_in_buf[3]~reg0 } { 0.0ns 0.0ns 1.03ns 3.581ns } { 0.0ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "data_buf.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/data_buf.v" 11 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.405 ns - Shortest register register " "Info: - Shortest register to register delay is 1.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_buf:inst4\|data_in_buf\[3\]~reg0 1 REG LC_X45_Y15_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X45_Y15_N3; Fanout = 1; REG Node = 'data_buf:inst4\|data_in_buf\[3\]~reg0'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "" { data_buf:inst4|data_in_buf[3]~reg0 } "NODE_NAME" } "" } } { "data_buf.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/data_buf.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.290 ns) + CELL(0.115 ns) 1.405 ns uart_if:inst3\|din\[3\] 2 REG LC_X45_Y13_N1 1 " "Info: 2: + IC(1.290 ns) + CELL(0.115 ns) = 1.405 ns; Loc. = LC_X45_Y13_N1; Fanout = 1; REG Node = 'uart_if:inst3\|din\[3\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "1.405 ns" { data_buf:inst4|data_in_buf[3]~reg0 uart_if:inst3|din[3] } "NODE_NAME" } "" } } { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 8.19 % " "Info: Total cell delay = 0.115 ns ( 8.19 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.290 ns 91.81 % " "Info: Total interconnect delay = 1.290 ns ( 91.81 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "1.405 ns" { data_buf:inst4|data_in_buf[3]~reg0 uart_if:inst3|din[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.405 ns" { data_buf:inst4|data_in_buf[3]~reg0 uart_if:inst3|din[3] } { 0.0ns 1.29ns } { 0.0ns 0.115ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 16 -1 0 } }  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "12.579 ns" { mclk div_4:inst2|acc[12] uart_if:inst3|cnt[3] uart_if:inst3|din[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.579 ns" { mclk mclk~out0 div_4:inst2|acc[12] uart_if:inst3|cnt[3] uart_if:inst3|din[3] } { 0.0ns 0.0ns 1.03ns 3.58ns 3.919ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "7.726 ns" { mclk div_4:inst2|acc[12] data_buf:inst4|data_in_buf[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.726 ns" { mclk mclk~out0 div_4:inst2|acc[12] data_buf:inst4|data_in_buf[3]~reg0 } { 0.0ns 0.0ns 1.03ns 3.581ns } { 0.0ns 1.469ns 0.935ns 0.711ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "1.405 ns" { data_buf:inst4|data_in_buf[3]~reg0 uart_if:inst3|din[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.405 ns" { data_buf:inst4|data_in_buf[3]~reg0 uart_if:inst3|din[3] } { 0.0ns 1.29ns } { 0.0ns 0.115ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "div_256:inst1\|clk reset mclk 6.701 ns register " "Info: tsu for register \"div_256:inst1\|clk\" (data pin = \"reset\", clock pin = \"mclk\") is 6.701 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.874 ns + Longest pin register " "Info: + Longest pin to register delay is 9.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns reset 1 PIN PIN_240 43 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 43; PIN Node = 'reset'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "" { reset } "NODE_NAME" } "" } } { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 88 24 192 104 "reset" "" } { 80 192 352 96 "reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.532 ns) + CELL(0.867 ns) 9.874 ns div_256:inst1\|clk 2 REG LC_X9_Y13_N7 59 " "Info: 2: + IC(7.532 ns) + CELL(0.867 ns) = 9.874 ns; Loc. = LC_X9_Y13_N7; Fanout = 59; REG Node = 'div_256:inst1\|clk'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "8.399 ns" { reset div_256:inst1|clk } "NODE_NAME" } "" } } { "div_256.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/div_256.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.342 ns 23.72 % " "Info: Total cell delay = 2.342 ns ( 23.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.532 ns 76.28 % " "Info: Total interconnect delay = 7.532 ns ( 76.28 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "9.874 ns" { reset div_256:inst1|clk } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.874 ns" { reset reset~out0 div_256:inst1|clk } { 0.000ns 0.000ns 7.532ns } { 0.000ns 1.475ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "div_256.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/div_256.v" 5 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 3.210 ns - Shortest register " "Info: - Shortest clock path from clock \"mclk\" to destination register is 3.210 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_153 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 21; CLK Node = 'mclk'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 72 24 192 88 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.711 ns) 3.210 ns div_256:inst1\|clk 2 REG LC_X9_Y13_N7 59 " "Info: 2: + IC(1.030 ns) + CELL(0.711 ns) = 3.210 ns; Loc. = LC_X9_Y13_N7; Fanout = 59; REG Node = 'div_256:inst1\|clk'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "1.741 ns" { mclk div_256:inst1|clk } "NODE_NAME" } "" } } { "div_256.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/div_256.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 67.91 % " "Info: Total cell delay = 2.180 ns ( 67.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.030 ns 32.09 % " "Info: Total interconnect delay = 1.030 ns ( 32.09 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "3.210 ns" { mclk div_256:inst1|clk } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.210 ns" { mclk mclk~out0 div_256:inst1|clk } { 0.000ns 0.000ns 1.030ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "9.874 ns" { reset div_256:inst1|clk } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.874 ns" { reset reset~out0 div_256:inst1|clk } { 0.000ns 0.000ns 7.532ns } { 0.000ns 1.475ns 0.867ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "3.210 ns" { mclk div_256:inst1|clk } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.210 ns" { mclk mclk~out0 div_256:inst1|clk } { 0.000ns 0.000ns 1.030ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}