ps2_keyboard_interface.tan.qmsg

实现PS/2接口与RS-232接口的数据传输

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "mclk " "Info: Assuming node \"mclk\" is an undefined clock" {  } { { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 72 24 192 88 "mclk" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "mclk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "uart_if:inst3\|uart:U1\|rcvr:u1\|clkdiv\[3\] " "Info: Detected ripple clock \"uart_if:inst3\|uart:U1\|rcvr:u1\|clkdiv\[3\]\" as buffer" {  } { { "../src/ref2/rcvr.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/rcvr.v" 37 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|uart:U1\|rcvr:u1\|clkdiv\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "uart_if:inst3\|cnt\[3\] " "Info: Detected ripple clock \"uart_if:inst3\|cnt\[3\]\" as buffer" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 27 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|cnt\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "uart_if:inst3\|wrn " "Info: Detected ripple clock \"uart_if:inst3\|wrn\" as buffer" {  } { { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 17 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|wrn" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "div_4:inst2\|acc\[12\] " "Info: Detected ripple clock \"div_4:inst2\|acc\[12\]\" as buffer" {  } { { "../src/ref2/div_4.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/div_4.v" 5 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "div_4:inst2\|acc\[12\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "div_256:inst1\|clk " "Info: Detected ripple clock \"div_256:inst1\|clk\" as buffer" {  } { { "div_256.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/div_256.v" 5 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "div_256:inst1\|clk" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\] " "Info: Detected ripple clock \"uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\]\" as buffer" {  } { { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 31 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\]" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "mclk register uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[0\] register uart_if:inst3\|uart:U1\|txmit:u2\|tsr\[0\] 71.85 MHz 13.918 ns Internal " "Info: Clock \"mclk\" has Internal fmax of 71.85 MHz between source register \"uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[0\]\" and destination register \"uart_if:inst3\|uart:U1\|txmit:u2\|tsr\[0\]\" (period= 13.918 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.237 ns + Longest register register " "Info: + Longest register to register delay is 2.237 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[0\] 1 REG LC_X27_Y14_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y14_N2; Fanout = 1; REG Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[0\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "" { uart_if:inst3|uart:U1|txmit:u2|tbr[0] } "NODE_NAME" } "" } } { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.499 ns) + CELL(0.738 ns) 2.237 ns uart_if:inst3\|uart:U1\|txmit:u2\|tsr\[0\] 2 REG LC_X26_Y12_N6 2 " "Info: 2: + IC(1.499 ns) + CELL(0.738 ns) = 2.237 ns; Loc. = LC_X26_Y12_N6; Fanout = 2; REG Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|tsr\[0\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "2.237 ns" { uart_if:inst3|uart:U1|txmit:u2|tbr[0] uart_if:inst3|uart:U1|txmit:u2|tsr[0] } "NODE_NAME" } "" } } { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns 32.99 % " "Info: Total cell delay = 0.738 ns ( 32.99 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.499 ns 67.01 % " "Info: Total interconnect delay = 1.499 ns ( 67.01 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "2.237 ns" { uart_if:inst3|uart:U1|txmit:u2|tbr[0] uart_if:inst3|uart:U1|txmit:u2|tsr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.237 ns" { uart_if:inst3|uart:U1|txmit:u2|tbr[0] uart_if:inst3|uart:U1|txmit:u2|tsr[0] } { 0.000ns 1.499ns } { 0.000ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.461 ns - Smallest " "Info: - Smallest clock skew is -4.461 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 12.636 ns + Shortest register " "Info: + Shortest clock path from clock \"mclk\" to destination register is 12.636 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_153 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 21; CLK Node = 'mclk'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 72 24 192 88 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns div_4:inst2\|acc\[12\] 2 REG LC_X8_Y13_N6 31 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N6; Fanout = 31; REG Node = 'div_4:inst2\|acc\[12\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "1.965 ns" { mclk div_4:inst2|acc[12] } "NODE_NAME" } "" } } { "../src/ref2/div_4.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/div_4.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.614 ns) + CELL(0.935 ns) 7.983 ns uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\] 3 REG LC_X10_Y13_N2 15 " "Info: 3: + IC(3.614 ns) + CELL(0.935 ns) = 7.983 ns; Loc. = LC_X10_Y13_N2; Fanout = 15; REG Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|clkdiv\[3\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "4.549 ns" { div_4:inst2|acc[12] uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] } "NODE_NAME" } "" } } { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.942 ns) + CELL(0.711 ns) 12.636 ns uart_if:inst3\|uart:U1\|txmit:u2\|tsr\[0\] 4 REG LC_X26_Y12_N6 2 " "Info: 4: + IC(3.942 ns) + CELL(0.711 ns) = 12.636 ns; Loc. = LC_X26_Y12_N6; Fanout = 2; REG Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|tsr\[0\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "4.653 ns" { uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] uart_if:inst3|uart:U1|txmit:u2|tsr[0] } "NODE_NAME" } "" } } { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns 32.05 % " "Info: Total cell delay = 4.050 ns ( 32.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.586 ns 67.95 % " "Info: Total interconnect delay = 8.586 ns ( 67.95 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "12.636 ns" { mclk div_4:inst2|acc[12] uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] uart_if:inst3|uart:U1|txmit:u2|tsr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.636 ns" { mclk mclk~out0 div_4:inst2|acc[12] uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] uart_if:inst3|uart:U1|txmit:u2|tsr[0] } { 0.000ns 0.000ns 1.030ns 3.614ns 3.942ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 17.097 ns - Longest register " "Info: - Longest clock path from clock \"mclk\" to source register is 17.097 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_153 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 21; CLK Node = 'mclk'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "" { mclk } "NODE_NAME" } "" } } { "ps2_keyboard.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/ps2_keyboard.bdf" { { 72 24 192 88 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns div_4:inst2\|acc\[12\] 2 REG LC_X8_Y13_N6 31 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N6; Fanout = 31; REG Node = 'div_4:inst2\|acc\[12\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "1.965 ns" { mclk div_4:inst2|acc[12] } "NODE_NAME" } "" } } { "../src/ref2/div_4.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/div_4.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.580 ns) + CELL(0.935 ns) 7.949 ns uart_if:inst3\|cnt\[3\] 3 REG LC_X44_Y13_N5 30 " "Info: 3: + IC(3.580 ns) + CELL(0.935 ns) = 7.949 ns; Loc. = LC_X44_Y13_N5; Fanout = 30; REG Node = 'uart_if:inst3\|cnt\[3\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "4.515 ns" { div_4:inst2|acc[12] uart_if:inst3|cnt[3] } "NODE_NAME" } "" } } { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.919 ns) + CELL(0.935 ns) 12.803 ns uart_if:inst3\|wrn 4 REG LC_X45_Y13_N7 8 " "Info: 4: + IC(3.919 ns) + CELL(0.935 ns) = 12.803 ns; Loc. = LC_X45_Y13_N7; Fanout = 8; REG Node = 'uart_if:inst3\|wrn'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "4.854 ns" { uart_if:inst3|cnt[3] uart_if:inst3|wrn } "NODE_NAME" } "" } } { "../src/ref2/uart_if.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/uart_if.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.583 ns) + CELL(0.711 ns) 17.097 ns uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[0\] 5 REG LC_X27_Y14_N2 1 " "Info: 5: + IC(3.583 ns) + CELL(0.711 ns) = 17.097 ns; Loc. = LC_X27_Y14_N2; Fanout = 1; REG Node = 'uart_if:inst3\|uart:U1\|txmit:u2\|tbr\[0\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "4.294 ns" { uart_if:inst3|wrn uart_if:inst3|uart:U1|txmit:u2|tbr[0] } "NODE_NAME" } "" } } { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.985 ns 29.16 % " "Info: Total cell delay = 4.985 ns ( 29.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.112 ns 70.84 % " "Info: Total interconnect delay = 12.112 ns ( 70.84 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "17.097 ns" { mclk div_4:inst2|acc[12] uart_if:inst3|cnt[3] uart_if:inst3|wrn uart_if:inst3|uart:U1|txmit:u2|tbr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "17.097 ns" { mclk mclk~out0 div_4:inst2|acc[12] uart_if:inst3|cnt[3] uart_if:inst3|wrn uart_if:inst3|uart:U1|txmit:u2|tbr[0] } { 0.000ns 0.000ns 1.030ns 3.580ns 3.919ns 3.583ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "12.636 ns" { mclk div_4:inst2|acc[12] uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] uart_if:inst3|uart:U1|txmit:u2|tsr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.636 ns" { mclk mclk~out0 div_4:inst2|acc[12] uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] uart_if:inst3|uart:U1|txmit:u2|tsr[0] } { 0.000ns 0.000ns 1.030ns 3.614ns 3.942ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "17.097 ns" { mclk div_4:inst2|acc[12] uart_if:inst3|cnt[3] uart_if:inst3|wrn uart_if:inst3|uart:U1|txmit:u2|tbr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "17.097 ns" { mclk mclk~out0 div_4:inst2|acc[12] uart_if:inst3|cnt[3] uart_if:inst3|wrn uart_if:inst3|uart:U1|txmit:u2|tbr[0] } { 0.000ns 0.000ns 1.030ns 3.580ns 3.919ns 3.583ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 26 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 27 -1 0 } } { "../src/ref2/txmit.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/src/ref2/txmit.v" 26 -1 0 } }  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "2.237 ns" { uart_if:inst3|uart:U1|txmit:u2|tbr[0] uart_if:inst3|uart:U1|txmit:u2|tsr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.237 ns" { uart_if:inst3|uart:U1|txmit:u2|tbr[0] uart_if:inst3|uart:U1|txmit:u2|tsr[0] } { 0.000ns 1.499ns } { 0.000ns 0.738ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "12.636 ns" { mclk div_4:inst2|acc[12] uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] uart_if:inst3|uart:U1|txmit:u2|tsr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.636 ns" { mclk mclk~out0 div_4:inst2|acc[12] uart_if:inst3|uart:U1|txmit:u2|clkdiv[3] uart_if:inst3|uart:U1|txmit:u2|tsr[0] } { 0.000ns 0.000ns 1.030ns 3.614ns 3.942ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/ps2_keyboard_interface_cmp.qrpt" Compiler "ps2_keyboard_interface" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/db/KEYBAORD.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EP1C12/PS2_RS232/Proj/" "" "17.097 ns" { mclk div_4:inst2|acc[12] uart_if:inst3|cnt[3] uart_if:inst3|wrn uart_if:inst3|uart:U1|txmit:u2|tbr[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "17.097 ns" { mclk mclk~out0 div_4:inst2|acc[12] uart_if:inst3|cnt[3] uart_if:inst3|wrn uart_if:inst3|uart:U1|txmit:u2|tbr[0] } { 0.000ns 0.000ns 1.030ns 3.580ns 3.919ns 3.583ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0}