proj.tan.qmsg

LCD1602显示源代码 1。源文件保存在src目录

{ "Info" "ITDB_FULL_TCO_RESULT" "clk LCD_D\[1\] lcd:inst\|counter\[1\] 39.192 ns register " "Info: tco from clock \"clk\" to destination pin \"LCD_D\[1\]\" through register \"lcd:inst\|counter\[1\]\" is 39.192 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 22.147 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 22.147 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns div16:inst1\|count\[3\] 2 REG LC_X8_Y13_N4 17 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N4; Fanout = 17; REG Node = 'div16:inst1\|count\[3\]'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "1.965 ns" { clk div16:inst1|count[3] } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.608 ns) + CELL(0.935 ns) 7.977 ns lcd:inst\|clkcnt\[7\] 3 REG LC_X9_Y13_N2 3 " "Info: 3: + IC(3.608 ns) + CELL(0.935 ns) = 7.977 ns; Loc. = LC_X9_Y13_N2; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[7\]'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "4.543 ns" { div16:inst1|count[3] lcd:inst|clkcnt[7] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/lcd.vhd" 74 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.304 ns) + CELL(0.590 ns) 9.871 ns lcd:inst\|reduce_nor~372 4 COMB LC_X9_Y12_N5 1 " "Info: 4: + IC(1.304 ns) + CELL(0.590 ns) = 9.871 ns; Loc. = LC_X9_Y12_N5; Fanout = 1; COMB Node = 'lcd:inst\|reduce_nor~372'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "1.894 ns" { lcd:inst|clkcnt[7] lcd:inst|reduce_nor~372 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.413 ns) + CELL(0.442 ns) 10.726 ns lcd:inst\|reduce_nor~375 5 COMB LC_X9_Y12_N7 7 " "Info: 5: + IC(0.413 ns) + CELL(0.442 ns) = 10.726 ns; Loc. = LC_X9_Y12_N7; Fanout = 7; COMB Node = 'lcd:inst\|reduce_nor~375'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "0.855 ns" { lcd:inst|reduce_nor~372 lcd:inst|reduce_nor~375 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 12.423 ns lcd:inst\|clkdiv 6 REG LC_X8_Y12_N0 3 " "Info: 6: + IC(0.762 ns) + CELL(0.935 ns) = 12.423 ns; Loc. = LC_X8_Y12_N0; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "1.697 ns" { lcd:inst|reduce_nor~375 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/lcd.vhd" 76 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.125 ns) + CELL(0.935 ns) 17.483 ns lcd:inst\|clk_int 7 REG LC_X10_Y13_N2 20 " "Info: 7: + IC(4.125 ns) + CELL(0.935 ns) = 17.483 ns; Loc. = LC_X10_Y13_N2; Fanout = 20; REG Node = 'lcd:inst\|clk_int'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "5.060 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/lcd.vhd" 72 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.953 ns) + CELL(0.711 ns) 22.147 ns lcd:inst\|counter\[1\] 8 REG LC_X49_Y17_N2 13 " "Info: 8: + IC(3.953 ns) + CELL(0.711 ns) = 22.147 ns; Loc. = LC_X49_Y17_N2; Fanout = 13; REG Node = 'lcd:inst\|counter\[1\]'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "4.664 ns" { lcd:inst|clk_int lcd:inst|counter[1] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/lcd.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.952 ns 31.39 % " "Info: Total cell delay = 6.952 ns ( 31.39 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.195 ns 68.61 % " "Info: Total interconnect delay = 15.195 ns ( 68.61 % )" {  } {  } 0}  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "22.147 ns" { clk div16:inst1|count[3] lcd:inst|clkcnt[7] lcd:inst|reduce_nor~372 lcd:inst|reduce_nor~375 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "22.147 ns" { clk clk~out0 div16:inst1|count[3] lcd:inst|clkcnt[7] lcd:inst|reduce_nor~372 lcd:inst|reduce_nor~375 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[1] } { 0.000ns 0.000ns 1.030ns 3.608ns 1.304ns 0.413ns 0.762ns 4.125ns 3.953ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.442ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../src/lcd.vhd" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/lcd.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.821 ns + Longest register pin " "Info: + Longest register to pin delay is 16.821 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|counter\[1\] 1 REG LC_X49_Y17_N2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X49_Y17_N2; Fanout = 13; REG Node = 'lcd:inst\|counter\[1\]'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "" { lcd:inst|counter[1] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/lcd.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.319 ns) + CELL(0.590 ns) 1.909 ns lcd:inst\|char_addr~1495 2 COMB LC_X49_Y18_N5 4 " "Info: 2: + IC(1.319 ns) + CELL(0.590 ns) = 1.909 ns; Loc. = LC_X49_Y18_N5; Fanout = 4; COMB Node = 'lcd:inst\|char_addr~1495'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/" "" "1.909 ns" { lcd:inst|counter[1] lcd:inst|char_addr~1495 } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/src/lcd.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.160 ns) + CELL(0.590 ns) 3.659 ns lcd:inst\|LessThan~391 3 COMB LC_X49_Y17_N8 3 " "Info: 3: + IC(1.160 ns) + CELL(0.590 ns) = 3.659 ns; Loc. = LC_X49_Y17_N8; Fanout = 3; COMB Node = 'lcd:inst\|LessThan~391'" {  } { { "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" "" { Report "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/HSNISO V3.2/HSNISO V3.2/EP1C12/LCD1602/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/HSNISO V3.